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IIRC DVI is LVDS with a few 5V cmos lines for things like EDID data, so yes (mostly) but you will need to level shift the I2C if you want access to the EDID.
You will need to pick a part with sufficient high speed serdes and transceivers if you want to run at much above minimum rate, and will need some glue of transient/EMC and dc bias.
Pretty much anything with the high speed trancevers should have sufficient PLL resources for this.
I thought TMDS was a protocol thing (A form of 8b10 coding) rather then being an electrical standard thing, but I turns out I was wrong about the electrical standard in use, it is actually CML, which most FPGAs can also do, so no real problem there.
Yes, it's not CML (differential current driven with ground referred termination), it's current driven with 3.3V referred termination.
It's no big thing to make a level shifter that interfaces TDMS level to a FPGA supported differential standard. If it makes sense to do the TDMS decoding in FPGA is a different question.
Xilinx Spartan 3 and Spartan 6 has differential IOs with a common range supporting TDMS on some banks, they can receive DVI without separate level shifters.
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