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PLL problem with declaration

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DNA2683

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hi all


i build a project that have 1 PLL( via IP catalog), 1 counter, and a MUX.

i wrote a Top vhdl code ( for ll the connections between the components)- but im getting an error "

object "outclk_0" is used but not declared


outclk_0 - is the the PLL output pin.- i did declared the pll on the top...can someone help me ( i added my code)

Code: 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 


ENTITY  Top  IS
    PORT (
			Clock_50_in   : In std_logic; 
			KEY_1  : In std_logic; 
			KEY_0  : In std_logic;
			result_out : out std_logic_vector(3 downto 0));
END Top;


ARCHITECTURE  structural  OF Top  IS


Component  counter   
port(
		clock_50 : in std_logic;
		count		: out std_logic_vector(31 downto 0)
);
End Component;
	
	
Component pll 
	port (
   	refclk   : in  std_logic := '0'; --  refclk.clk
    	rst      : in  std_logic := '0'; --   reset.reset
 		outclk_0 : out std_logic );
end Component;	


Component muxl 

	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		sel		   : IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	
end Component;	
	

Signal S1 : std_logic_vector(31 downto 0);
Signal S2 : std_logic_vector(3 downto 0);
Signal S3 : std_logic_vector(3 downto 0);
Signal S4 : std_logic;
Signal S5 : std_logic;


BEGIN



U1: counter
Port Map (clock_50 => S5 ,
		    count   => S1
	);
		 
U2: pll
Port Map (refclk => Clock_50_in,
		    rst   => S4,
		    outclk_0   => S5
				);
		 
		 
U3: muxl
Port Map (data0x => S2,
		    data1x   => S3,
		    sel   => KEY_0,
			 result   => result_out
				);
				
				
S2 <= S1(24 downto 21);
S3 <= S1(26 downto 23);
S4 <= not(KEY_1);
S5 <= outclk_0;	
	

END structural ;
 

I presume you get the error for this line
Code: 
S5 <= outclk_0;
It's useless, because outclk_0 is already conncted to S5 in the PLL instantiation. And yes, outclk_0 is not declared in the top entity.
 

FvM said:
I presume you get the error for this line
Code: 
S5 <= outclk_0;
It's useless, because outclk_0 is already conncted to S5 in the PLL instantiation. And yes, outclk_0 is not declared in the top entity.
Click to expand...

yes i get this error on this line :)

outclk_0 is a output pin from the PLL that i connected to the input clock_50 of the counter. -> outclk_0 connect internal in my FPGA

how do i solve this problem?
i added picture of the architecture
121212121.jpg
 

I saw the connection diag above and based on it I want to ask, why are you not connecting directly outclk_0 to clock_50 via portmap?
 

dpaul said:
I saw the connection diag above and based on it I want to ask, why are you not connecting directly outclk_0 to clock_50 via portmap?
Click to expand...

i tried to connect it directly but i got the same error...so i tried to connect it via signal (s5) -> but still i have the same error

i don't know what else i can do..
 

Hi,

You can try this.

Code: 
U2: pll
Port Map (refclk => Clock_50_in,
		    rst   => S4,
		    outclk_0   => S5
				);

In this instead of S5 use one more signal say temp and assign temp in port map and then use s5 <= temp;
 
Last edited by a moderator:
The reason why 

Code VHDL - [expand]
1
2
3
4

S2 <= S1(24 downto 21);  -- works because signal S1 is declared
S3 <= S1(26 downto 23);  -- works because signal S1 is declared
S4 <= not(KEY_1);            -- works because key_1 is declared in top entity
S5 <= outclk_0;                -- Does not work because outclk_0 is not declared


Try adding 
Code VHDL - [expand]
1
2
3

signal outclk_0 : std_logic;
-- instantiate with 
outclk_0 => outclk_0);


Then when you doing the 
Code VHDL - [expand]
1

S5 <= outclk_0;

it should work. This is a temp transition that amit was talking about

The main problem is that outclk_0 was never declared in this current level.
 
amit.kumar11 said:
Hi,

You are most welcome. Good to hear that your problem is solved.
Click to expand...

when im trying to do a compilation i get 4 errors:

Error (11802): Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 7 warnings
Error: Peak virtual memory: 1114 megabytes
Error: Processing ended: Tue Aug 04 16:11:16 2015
Error: Elapsed time: 00:00:15
Error: Total CPU time (on all processors): 00:00:15
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 10 warnings

what can be the problem?

thanks
 

the problem is that your design is too big for your device.
What are the errors?
 

my project include a SDC (timequest timing analyzer) - i didnt wrote it but i have to include it in my project. when i remove it the compilation pass...but when i include it in my project i get errors.

the code of the SDC is:

Code: 
create_clock -name "clock_50_in" -period 20.000ns [get_port{clock_50_in}]
derive_pll_clocks
derive_clock_uncertainty

telling the true i dont know what this file do
 

It tells the fitter and timing analyser that your clock is 50Mhz, and it derives any clocks that are generated from connected PLLs.
It shouldnt make a difference to the design and mean it wont fit.
 

TrickyDicky said:
It tells the fitter and timing analyser that your clock is 50Mhz, and it derives any clocks that are generated from connected PLLs.
It shouldnt make a difference to the design and mean it wont fit.
Click to expand...

so if i wont include this file in my project the design will not work?

if not-> how i can solve the problem?

thanks for the help
 

davida said:
so if i wont include this file in my project the design will not work?
Click to expand...
That is a relative statement. e.g.- Your design might work in simulation but it may fail in synthesis.
From your errors it seems you want to synthesize your design and you are also using an SDC file.

As TrickyDicky has mentioned, your design seems to be too big for the FPGA device used. Post the actual errors and not just the verbose "Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 10 warnings".
 

If it fits without using an SDC and does not fit after adding a clock constraint of 50 MHz, then that likely means the design isn't pipelined properly. A 50 MHz clock is slow compared to the performance of the typical low end Spartan 6 or Cyclone part. This means that there is probably a large amount of logic between registers and when Quartus II synthesizes the design to meet timing it has to replicate a lot of registers and perform excessive logic optimizations to try and meet the timing requirements. I suspect even if the part was big enough the design would likely fail timing.

To make any further assessments the rest of the design code would have to be posted.
 

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