Gapping a ferrite core for Full Bridge SMPS transformer?

Hello ,
We are designing a 1.7kW Full Bridge SMPS transformer using a PM62/49 core by Epcos TDK (N87 material).

We don’t want a gap in the core, but I believe We will have to have one because otherwise the change in the “saturation current” level {I(SAT)} varies too much as temperature changes….

As you know, the effective permeability (ue) of ungapped cores varies dramatically with temperature (see attached graph from Epcos)..

For example, an ungapped PM62/49 ferrite core using N87 material (by Epcos TDK) has ue = 1400 at 25degC..
However, at 120degC, ue = 3800

Now Consider that I have a 20 turn primary….

Now…..L(pri) = (N^2)/reluctance
[where N = Number of primary turns)]

Where reluctance = (core length)/ (uo.ue.A)
[where A = core area, uo = permeability of free space, ue = effective permeability)

At ue = 1400; L(PRI) = 3.03mH
….and I(SAT) = (Bsat.A.N.)/L = 0.77 Amps

At ue = 3800; L(PRI) = 8.24mH
…..and I(SAT) = (Bsat.A.N)/L = 0.34 Amps


[where Bsat = 300mT (saturation flux density); A=Core area; N = turns; L = inductance]


We need to know exactly what is our saturation current, and we simply cannot tolerate this level of variation in the saturation current level. If we work to the lowest level of saturation current, then we would in any case end up with a too big a core, as we would need to increase the core size.

Therefore, we will add a gap to the centre leg of the core…(just 0.2mm)….this means that the ue value will not vary over temperature, as is seen in Epcos graph attached.

Do you agree we need the gap?

(The gap will also help in making the saturation characteristic much less sharp, meaning that if we encounter sudden overload etc, then we are more likely to be able to ‘catch it’ with the current sense before the SMPS blows up. Also, during transients, our error amplifier can saturate high, meaning that our duty cycle goes to absolute maximum, and this can result in runaway saturation of the core if it is not gapped.)

So do you agree that a gap (just a tiny one) is needed?


PM62/49 Ferrite core datasheet:
**broken link removed**

The attached shows “ue vs Temperature” for gapped and ungapped PM62/49 cores.

Once you get past the negative slope in Ue vs T , you can get thermal runaway . So if this cannot be controlled, a gap is needed for linearity.

treez said:

We need to know exactly what is our saturation current

Click to expand...

Why? How accurate do you have to be, relative to the primary current?

I have never heard of a gapped core in a full bridge transformer, except in the odd case where voltage mode control is used and therefore flux walking is possible. If you use CMC then I can't think of even a single reason for it. And with a full bridge converter you shouldn't be operating anywhere near saturation in the first place.

With a full bridge, the magnetising current is bipolar.....but at first it is not....and this is where you can fly off into saturation if you don't have the gap.............surely you agree that the saturation current gets less the hotter it gets for the 20 turns of the above winding?
I have tried to do the design of the transformer with PM62/49 and using the highest (hottest) value of permeability and you just simply cannot do it with that core...you are above the saturation current level.....you have to have the gap.

I am sure you agree with the mathematics of the post #1. For those 20 turns on that ungapped core, when the temperature rises up, the ue gets to 3800 and the saturation current level gets too low.

If you don't have a gap, you end up needing too big a core.

The saturation of N87 material is about 450mT, and I am way below that with my gapped design (I get 0.211T peak)

The fullbridge spec is
vin=390vdc, vout = 400vdc, pout=1750W, FSW=40KHZ.

I went for a duty cycle of about 0.7 and got the turns ration that gave that.

You just cannot do this with a PM62/49 in ungapped form.
Put the 0.2mm gap in there, and you get an AL value of 2297nH/N^2 and it does the job.

With the ungapped way, I ended up needing loads of turns, (toomuch winding loss) and even then was too near I(sat).

We wouldn't be gapping it unless we really needed to...it costs more for a start.

The thread sounds like a replay of the discussion in a previous thread https://www.edaboard.com/threads/340530/

It's been said by most contributors to the previous thread that generally unusual to have a gapped core for forward converters, and the same applies of course to bridge converters.

I don't see how saturation current would be a relevant parameter in bridge converter transformer design.

It's often said that a small gap can help against "flux walking", but it's more preferred to cancel current asymmetries by control means. See e.g. Magnetics Design 4 - Power Transformer Design www.ti.com/lit/ml/slup126/slup126.pdf

A full bridge converter needs no gapping in the Tx - AT ALL - it may need a DC blocking cap for volt mode control - but nothing is needed for peak current mode control.
Gapping is a poor way to partially fix a bad control system...

- - - Updated - - -

For simple PWM on a full bridge, having a guaranteed dead time of 3-5% will give enough reset time on the Tx to cure most offset problems, for phase shift, peak current mode is the usual control method - no gap needed.

Yup.
Orson has nailed it...

The reality is that normal lapping is already a gapped core.

thanks but I think the maths of post#1 answers all of the replies here. If you see the difference in I(SAT) at the different temperatures....would you work to the higher temperature I(SAT) level....if you would , then you would be using a much bigger core than somebody who gapped it.

but I think the maths of post#1 answers all of the replies here

Click to expand...

So you say, all existing designs and text books are wrong, you discovered the ultimate math of converter transformers?

But you didn't yet answer the simple question how Isat comes into play in your full bridge converter design.

It's essentially the same thing as in your previous forward converter thread, magnetizing current is only a small fraction of the total primary current, even a large change due to temperature or core assembly variations doesn't actually matter.

No your conclusion doesn't follow from those calculations, at all. You don't actually demonstrate why saturation might be more likely to occur with no gap (It doesn't because your saturation volt-time product is independent of reluctance).

If you're totally convinced you're correct, and aren't willing to engage with any counterarguments, then why even bother posting a thread?

you appear to be saying that your full bridge transformer will have peak B nowhere near 300mT?

Based on nomographs I've seen from manufacturers, the optimal Bmax for push pull transformers (like full bridge) is never above 200mT. At higher switching frequency, Bmax should be even lower. This is because core losses tend to increase faster vs frequency and ripple than conduction losses do.

edit: to give an example, take the EPCOS databook you linked in another thread. It lists the performance factor (PF) of various materials vs frequency (page 49), where PF is equal to the product of the switching frequency and the Bmax which gives a specific power loss of 300kW/m^3. For N87, at 30kHz PF=10,000 (so Bmax=333mT) but at 100kHz PF=18,000 (so Bmax=180mT). This doesn't give the optimal Bmax for efficiency (since this only accounts for core losses), but the real optimal Bmax will always be lower than these numbers. But the trend is similar.

EPCOS ferrite tool ends up with Bmax of about 275 mT for 40 kHz full bridge with PM62 core, based on 25 K core loss induced temperature rise.

Surely we must specify a temperature for these Bmax readings?...as you saw from my first post, for a given number of turns on a ungapped core, the Bmax will vary widely depending on temperature.

I believe you would see the problem of doing it with an ungapped core if you tried to do it with an ungapped PM62/49 core.

The spec is:-
full bridge
Vin = 390vdc
vout = 400vdc
fsw = 40khz (but you can choose if you wish)
pout = 1.75kw.

-when you try to do this with an ungapped PM62/49 core, you will see the problem I ran into , and will then realise. A gap is needed.

Treez, it does appear that you are running too many volt seconds on your designs, hence your trouble with Bsat, and your infatuation with gapping, there are loads of crappy ferrites out there that roll over at just > 100 deg C, simple answer, DON'T USE THEM... use 3F3 or better, N87, N67, 3C96 and then run a suitable Bmax for 40kHz (N27 will do for 40kHz) then all your problems will reduce....of course control systems that have non symmetric pulses applied to a Tx are a whole other issue...allowing plenty of dead time in your designs will mostly cure this...as it allows Tx reset.

treez said:

Surely we must specify a temperature for these Bmax readings?...as you saw from my first post, for a given number of turns on a ungapped core, the Bmax will vary widely depending on temperature.

Click to expand...

No, you did not demonstrate this. You showed Isat changing, which is not a problem for a full bridge transformer.

Treez, it does appear that you are running too many volt seconds on your designs, hence your trouble with Bsat

Click to expand...

I amusing N87, and am within the 275mT suggested by mtwieg. If you can do that with a non gapped pm62/49 core then I take my hat off, (spec is in #15), but I don't believe its possible.

at 40kHz your peak B should be 180mT.

Hello,
Finally , here is the proof that a Full Bridge SMPS ferrite transformer needs gapping. Do you agree?….
The peak B of this Full Bridge SMPS (with ETD49-3C94 core) goes up to 397mT at startup. At steady state, max load, the peak B is only 170mT.
The 397mT is too close to saturation for an ungapped core. This shows that Full Bridge SMPS transformers need to be gapped to avoid ‘flyaway’ saturation at startup.

LTspice simulation and pdf schematic attached.