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How can we reduce the delay in the data path? By logic change? Or by putting buffers in the data path?? Will addition of buffers increase the total delay of the path in all situations or is there any chance that it reduces the total delay?
Ur question is confusing. Addition of any element including buffers will only increase the delay. It will not bring the delay down. You can reduce the delay in the data path by a logic change or by using faster cells.
Method 5 and method 6 to fix set up violations suggests to add buffers in the datapath. According to the explanation they gave, it seems to be a working method. Are they practical solutions??
I will try to answer you question, but someone please correct me if I am wrong. I have no experience in VLSI and I am still a student.
Buffer is a back-to-back inverter with the first inverter being small and the second one being larger. So the logic preceding the buffer sees a lower gate capacitance(load cap for the logic preceding the inverter) while the second inverter of the buffer has a larger drive strength. So it is better to use buffers than inverters for two reasons.
1. Delay is proportional to L square and the length is reduced by adding buffers(same in the case of inverters as well)
2. Lower gate cap. seen by the driving cell( advantage of buffer over inverter)
Method 5 and method 6 to fix set up violations suggests to add buffers in the datapath. According to the explanation they gave, it seems to be a working method. Are they practical solutions??
Did you read the description (of 5 & 6) to see why it fixes the problem? (i.e. long wires have more capacitance and therefore slower transitions, adding a buffer improves the transition time as there is now something actively propagating the signal on the shorter half length wire)
@ads-ee: Of course their explanation seems to be convincing and working one. But my question is whether they are practically followed methods or just theoretical ones? While doing PnR, how often we encounter a situation that the tool gives us large wires between two buffers and insertion of a buffer in between them reduces the delay? To reduce the total delay, the additional delay inserted by the cell delay of the buffer should be less than the redcution in delay. Is this a common method?? I am not an expert in this and haven't ever faced such a situation!!
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