[SOLVED] Steaming Audio 44.1kHz Delta Sigma DAC --> FPGA

• FPGA:Spartan 6
• DAC CLK Freq: 300Mhz
• Bit Width: 16bits
• Sample Rate 44.1kHz

The inputs to the Delta adder are unsigned, the outputs of both adders are considered signed
numbers. The Delta Adder calculates the difference between the DAC input and the current DAC output, represented as a binary number. Since the DAC output is a single bit, it is “all or nothing”; i.e., either all zeroes or all ones.

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Code Verilog - [expand]
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‘timescale 100 ps / 10 ps
‘define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
 
module dac(DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [‘MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg [‘MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [‘MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [‘MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [‘MSBI+2:0] DeltaB; // B input of Delta adder
 
always @(SigmaLatch) DeltaB = {SigmaLatch[‘MSBI+2], SigmaLatch[‘MSBI+2]} << (‘MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
 
always @(posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      SigmaLatch <= #1 1’bl << (‘MSBI+1);
      DACout <= #1 1‘b0;
    end
  else
    begin
      SigmaLatch <== #1 SigmaAdder;
      DACout      <= #1 SigmaLatch[‘MSBI+2];
    end
end
 
endmodule

Dan Mills said:

You shouldn't be complementing, you should be offsetting all the samples by adding 32768 before feeding your DAC.
This way the zero signal output will be half rail and the audio can swing both ways.

I have not looked closely at the code, Verilog is not my thing.

Regards, Dan.

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Dan Mills said:

Well your input range is -32768 -> 32767 correct?

Your DAC expects to see 0 -> 65535, the addition of 32768 to your signed value (note +32768 needs 17 bits as a signed integer) will yield a value having a range of 0 -> 65535 (17 bits as a signed value) which you then convert to unsigned (16 bits), with audio silence being somewhere in the middle of that range.

Audio DACs all have an output corresponding to zero (audio sample value) input of mid scale, you then remove the DC component with a series cap.

If you think about it the process MUST be linear (anything else introduces mixing products), which addition is, but complement only some of the time most certainly is not.
If +1 produces output 20 & zero produces output 15 then -1 should surely produce output 10, not go back up to output 20, generally anytime you find yourself doing different things depending on the sign of a sample you are introducing a non linear element and that is usually not what you want.

Addition not xor!

Regards, Dan.

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