What happens if multiple interrupts are asserted to the PIC?

In CCS C Compiler it is possible to set a multitude of interrupts and assign an ISR to it. I want to know what happens if multiple interrupts occur at the same time or if another interrupt occurs before the current ISR has not finished execution.

For example, here is a list of some of the possible interrupts:

Analog to digital conversion complete
Analog to digital conversion timeout
Bus collision
Pushbutton
Capture or Compare on unit 1
Capture or Compare on unit 2
Comparator detect
I2C interrupt (only on 14000)
LCD activity
Low voltage detected
Parallel Slave Port data in
Port B any change on B4-B7

What if e.g 'Low voltage detected' interrupt occurs while the 'Analog to digital conversion complete' is still executing?
Will the later interrupts be executed in the order they occured once the current ISR is finish executing?
Is it possible to assign some sort of "index" to all ISRs to tell the PIC which is more important than others?

pic18 and up, allow 2 priorities to be defined (high and low). If two high priority interrupts occur almost simultaneously, the isr will handle them with the sequence that you handle them in the isr routine.
If a high priority irq happen when in a low priority isr, the low priority isr will have to wait till high isr executes and terminates.

ps. some irq signals can be handled only by high isr routine (are always high priority)

@xenos, in CCS PIC C one uses #INT_xxx directive to associate an ISR with an interrupt source e.g #INT_TIMER0. Therefore, there isn't a single ISR routine which is associated with all high priority ISRs and when launched looks at the interrupt flags to determine the interrupt source and then executes the relevant ISR for that interrupt. Therefore, your answer is not completely clear to me.

PIC mC does not execute CSS C version or any other high level language. It executes machine code and only.
It does not matter if the compiler allow you to create a function for every interrupt source.
The hex output code will contain code designed for the specific PIC mC.
You have not state what PIC mC you are talking about, so I will post a part of the PIC18 family documentation:

The PIC18F2455/2550/4455/4550 devices have
multiple interrupt sources and an interrupt priority
feature that allows each interrupt source to be assigned
a high priority level or a low priority level. The high
priority interrupt vector is at 000008h and the low
priority interrupt vector is at 000018h. High priority
interrupt events will interrupt any low priority interrupts
that may be in progress.

Click to expand...

source:
https://ww1.microchip.com/downloads/en/devicedoc/39632c.pdf
chapter 9.0 (interrupts), page 99

- - - Updated - - -

For PIC16F8XX there is only one interrupt service routine:

When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits

Click to expand...

source: https://ww1.microchip.com/downloads/en/DeviceDoc/30292c.pdf
Chapter 12.10, page 131

OK, it is clear now. The CCS compiler gave me an impression which now I understand was wrong.