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DC synthesis - setup has higher priority than hold violation?

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Hi,

In general, right after synthesis by DC (before ECO)
the number of hold violations is much greater than setup violations.

Is this because DC tool puts higher priority on setup than hold optimization?

Thanks,
dl
 

Typically, you don't worry about hold fixing during logic synthesis. You'd only try to fix hold violations in P&R after CTS. So yes.
 
You can fix the hold violations by adding delay elements in the data path during PnR flow. You will get the true status of the hold violations only after the CTS stage. So we give importance to hold fixing post CTS and set violations are considered in the earlier stages itself.
 

hold time fixing is a necessary evil as it doesn't impact the speed or functionality of the design. while setup impacts the quality of result of the design. So once your timing is met along with functionality ...hold time needs to be fixed as it is a must have....

This is the simple explanation but now a days people are using fix hold early by using circuit design techniques ....for functional path...look at "lock up latch"....the idea can be used to fix functional hold times also using this technique.....
 

The Synthesis tool wont look at the Hold at all, because Hold can be optimized/fixed during the PD ( mainly after CTS ).
 
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