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[SOLVED] Problems With VHDL Memory Access Code Module

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MSAKARIM

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I have a memory initialized from text file ,the contents of the text file is binary data
I used LFSR to store this data in my memory with random address
then i need to make some operations on this data then back it to the memory
but the operations not performed and i cant know the error because during compiling no errors appear
this is the code of the operation ( its an embedding operation < call data from memory then exchange one bit from it with one from another data ) 
Code VHDL - [expand]
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entity Embedding_Module is
    port(clk,rst:in bit;
        datain :in bit_vector (127 downto 0);
         PixelOut:out bit_vector (7 downto 0));
    end Embedding_Module;
    
    architecture st of Embedding_module is
      component inst_memory port(clk,rst : in bit;
           inst: OUT bit_VECTOR(7 downto 0));end component; 
   signal PixelIn :bit_vector(7 downto 0);
 begin
            G1:inst_memory port map(clk,rst,PixelIn);
        process (clk)
begin
   
            if (clk'event and clk='1') then
        g2:for i in 0 to 127 loop
          pixelout<= PixelIn(7 downto 1) & datain(i);
        end loop;  
       end if;
        
end process; 
    end st;

__-
during simulation pixelout respond one time at i=0 and be constant

how can i solve this problem!?
 
Last edited by a moderator:

Your problem is because you are using a for loop in a temporal fashion (software style). A for loop in VHDL is unrolled completely so what you have is every possible index of pixelout exists in parallel.
Code: 
pixelout <= PixelIn(7 downto 1) & datain(0);
pixelout <= PixelIn(7 downto 1) & datain(1);
...
pixelout <= PixelIn(7 downto 1) & datain(127);
and only the last one takes effect, i.e.:
Code: 
pixelout <= PixelIn(7 downto 1) & datain(127);
 
First of all, I'm not sure that loop is going to do what you want it to do. I think what it will do is run that loop 128 times each clock cycle. That's probably not what you were intending. Putting the loop statement inside a clocked process is a little messy.
 
But i need every value of pixelout not the last only
pixelin which called from memory has different value at each clock < i need all this values ,as every value i'll embed in it one bit from datain

- - - Updated - - -

I have a memory contains pixels's values of a certain image saved with random addresses , I need to call this pixels randomly and embed in every one of it one bit from datain and then back it to the memory
Now my problem in embedding operations.
 

Remove the for loop and implement an upcounter which counts on the same clock. Use the counter value to index and select the datain bit.
 
Did you draw a circuit diagram of your intended circuit before you wrote the VHDL?
 
yes i did that

- - - Updated - - -

I need more explain please
 

MSAKARIM said:
yes i did that

- - - Updated - - -

I need more explain please
Click to expand...

You need to understand how VHDL works. A signal inside a clocked process gets updated once per clock cycle. What you've essentially done is created a signal that gets changed 128 times per clock cycle so that what ultimately 'comes out' of the process is the 128th value.

As sharath explained, one way to accomplish what you want is to increment an address counter that indexes your memory.
 

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