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2D matrix input in VHDL for FFT

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shan14

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Hi

I have vhdl code for 1D FFT it runs perfect.Now I want to convert it to 2D
My question is do I need input in matrix form for the 2D fft??

I am using 16 inputs for 1D fft which are coming one by one. so for converting the code to 2D fft
do I need to change the input or can I use the same input which was used for 1D fft
 


Hi

thanks for your reply

I have to implement 2D fft in VHDL . I have 1D fft vhdl code, now how do I convert it to 2D fft??
 

shan14 said:
Hi

thanks for your reply

I have to implement 2D fft in VHDL . I have 1D fft vhdl code, now how do I convert it to 2D fft??
Click to expand...

I believe you are using shift registers in your 1D code. You need to store the shift register value in row buffers. if you are using 3x3 kernel then you need 2 row buffers to store previous row values. The document which I have shared illustrates this method. If the kernel is symmetrical then you can split vertical and horizontal filters to save fpga resources.
 

Hi

Can I apply below input that has been applied to 1D fft, to the 2D fft??
the input is like array of vector form i.e.

0000000000010000
1000111000101001
0100101101000001
0011010011100101
0101001100101101
0001110000110001
1101010000001011
0011111100110010
0100111010001111
0010000001011010
0010111010100111
0010110000000010
1001001110000010
0001110000100100
1011101110000101
0010010101001100
1101010010111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
 

I sure you could - you just need to use it in the correct way.
 

shan14 said:
Hi

Can I apply below input that has been applied to 1D fft, to the 2D fft??
the input is like array of vector form i.e.

0000000000010000
1000111000101001
0100101101000001
0011010011100101
0101001100101101
0001110000110001
1101010000001011
0011111100110010
0100111010001111
0010000001011010
0010111010100111
0010110000000010
1001001110000010
0001110000100100
1011101110000101
0010010101001100
1101010010111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
Click to expand...

yes you can apply this input one after another to your filter and then do the required convolution.
 
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But after applying this input to 1D fft , what is the process for calculating 2D FFT ???
what should I do to the output coming from 1D FFT??
 

You need to design a 2D filter to do your 2D FFT. you send the data through the 1D filter and then save the 1D filtered data in a buffer and then repeat the same depending on the size of your filter kernel. Check the Xilinx document which I have attached in my first post.
 
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Hi

thanks

I had 16 input for my 1d fft ,Now for 2D fft I had assumed that 16 input into 4*4 matrix.but they are defined in the same way as it was for fft 1D.
Now I am calculating the 1D fft then transposing the 1D fft output then again calculating the 1D fft on those and at last again transposing them.

suppose below is my output of 16 point 1D fft.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16

I am assuming above as
1 5 9 13
2 6 10 14
3 7 11 15
4 8 12 16

Now for transposing I am doing like this
1
5
9
13
2
6
10
14
3
7
11
15
4
8
12
16

and this transposed output I am applying as the input to the again to the fft
and at last again transposing.

Is this correct???
please help


How to store the dta in buffer using vhdl ??
 

Where are these values coming from? are they just a text file? you can read them in how you like as long as you put them in the right place.
To define a 2d array, you can simply declare an array type:

type my_2d_fft_array_t is array(0 to 3, 0 to 3) of integer;

Or whtever other type you want.
 
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shan14 said:
Hi

thanks

I had 16 input for my 1d fft ,Now for 2D fft I had assumed that 16 input into 4*4 matrix.but they are defined in the same way as it was for fft 1D.
Now I am calculating the 1D fft then transposing the 1D fft output then again calculating the 1D fft on those and at last again transposing them.

suppose below is my output of 16 point 1D fft.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16

I am assuming above as
1 5 9 13
2 6 10 14
3 7 11 15
4 8 12 16

Now for transposing I am doing like this
1
5
9
13
2
6
10
14
3
7
11
15
4
8
12
16

and this transposed output I am applying as the input to the again to the fft
and at last again transposing.

Is this correct???
please help


How to store the dta in buffer using vhdl ??
Click to expand...

Well after getting your 1D output, store the first first 4 output values in a array buffer_1 of size 4. Then the next 4 output values in array buffer_2. So you need 3 array buffers if your 2D matrix kernel is 4x4 size. 3 buffers. Similar to the Xilinx document attached. The diagram clearly explains how to pass the output values after row filtering and storing them in buffers at the same time. You have done now filtering only in one direction.
 
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Hi

How to create 2D memory in VHDL??
because now I am doing fft on 16*16 matrix so these outputs should be stored in memory .
 

You need to remember that 2D arrays are only a concept in VHDL, not the actual hardware. You need now to think about how your circuit is going to look, not asking question how to write the VHDL. VHDL is a hardware description language, not a programming language.

Get out some paper and draw the circuit you want to acheive. Or even better, draw it in visio or powerpoint and write it all up in a document BEFORE you write any VHDL (this is what is done with real engineering in real companies).
 

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
 
entity sync_ram is
  port 
  (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector(7 downto 0);
    datain  : in  std_logic_vector(15 downto 0);
    dataout : out std_logic_vector(15 downto 0)
  );
end entity sync_ram;
 
architecture RTL of sync_ram is
    
  type ram_type is array(0 to 15,0 to 15) of std_logic_vector(15 downto 0);
  signal ram : ram_type;
  signal read_address : std_logic_vector(7 downto 0);
 
begin
 
  RamProc: process(clock) is
 
  begin
    if rising_edge(clock) then
      if we = '1' then
        ram(to_integer(unsigned(address))) <= datain;
      end if;
      read_address <= address;
    end if;
  end process RamProc;
 
  dataout <= ram(to_integer(unsigned(read_address)));
 
end architecture RTL;


I have written this code for storing 16*16 matrix
I am getting error while sImulating,

what should I do to store these 16*16 values?
also I should be able to access those values
 
Last edited by a moderator:

First of all - please use code or syntax tags for your code.

Your ram is now 2 dimensions, so you need two addresses, not 1. You'll need to separate the two 4 bits of the addres to access the array:

Code VHDL - [expand]
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signal row_i : integer range ram_type'range(1);
signal col_i : integer range ram_type'range(2);
 
.....
 
RamProc: process(clock) is
   variable row, col    : integer;
begin
    if rising_edge(clock) then
    
        row := to_integer( unsigned( address(7 downto 4) ));
        col := to_integer( unsigned( address(3 downto 0) ));
        
        if we = '1' then
            ram(row, col) <= datain;
        end if;
    
        row_i <= row;
        col_i <= col;
    end if;
end process RamProc;
 
 
dataout     <= ram(row_i, col_i);
 
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Hi

now I am facing problem with adding input into this ram because of the 'address' port.
because value coming into this ram are the output values from fft block. So, how do I give the address for that data .

I have port mapped the ram.i.e. output of FFT is fed as a input to ram but how can I give the address??
 

are u using an IP from the core generator or how?? You can port map the input to the address port or you can assign the address when you are inputting into the RAM and have counters to increment the address and also count the number of input data arriving. This way you can monitor the signals.

If you could post your code, it would be helpful to debug it.
 

Post your code.
It may just be a type conversion issue.
 

Hi

address issue resoved, I want to ask about 2D fft.

can we say that 2D fft of 16 point FFT is nothing but 16 times FFT calculation of 16 point FFT.??
 

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