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[STA] SDF or SPEF -> which one to use? Why?

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ivlsi

ivlsi

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Hi All,

What file is used for STA - SDF or SPEF?

I know what SDF is used for Gate Level Simulations. What's about SPEF? When should it be used?

As for SPEF file, does it contain R and C values for all or just a certain corner?

Why SDF file cannot be used for STA instead of SPEF file?

Thank you!
 

SPEF is usually used for STA. That is because it consists of parasitics data also. SDF does not include parasitics info.
 
sharath666 said:
SPEF is usually used for STA. That is because it consists of parasitics data also. SDF does not include parasitics info.
Click to expand...

Can you explain this in a little more detail ?
 

By parasitics I mean the resistance and capacitance values (R&C) of the nets which play a major role in determining the timing performance of a circuit. A SPEF includes this as well the flop delays and gate delays. An SDF includes only the flop delays and gate delays and is therefore inaccurate.
 

SPEF file has R and C values which the STA tool uses to calculate and arrive at cell and net delays and compute the crosstalk information.

SDF has annotated delays and cells are annotated with the delays. STA tool just has to annotate these delays and there is no computation involved.
Usually SDF is written out from STA tools as an input for simulation, and SPEF is read in to STA tool so that it can compute the delays.

Cheers
G1
 

sharath666 said:
By parasitics I mean the resistance and capacitance values (R&C) of the nets which play a major role in determining the timing performance of a circuit. A SPEF includes this as well the flop delays and gate delays. An SDF includes only the flop delays and gate delays and is therefore inaccurate.
Click to expand...

I have SDF file from design compiler , SPEF and SDF file from ICC , so I need to give only SPEF file for primetime along with dc netlist?
 

DC SDF is different from ICC SDF. Buffers in the clock path are not considered in DC SDF.
 
DC will use wireload model. But Dc Topo(used in the right way) & ICC will have correct delays.
 

sharath666 said:
DC will use wireload model. But Dc Topo(used in the right way) & ICC will have correct delays.
Click to expand...

So why we go for SPEF file , if SDF file from ICC is giving correct interconnect delay, gate delay etc .
 

I think you are not understanding what I am trying to say. Go through the entire post again on why SPEF is better than SDF.
 

sharath666 said:
I think you are not understanding what I am trying to say. Go through the entire post again on why SPEF is better than SDF.
Click to expand...

From your point the delay is calculated from R & C parasatics in SPEF file .
But in SDF file from ICC also contain interconnect and gate delay (After P & R).
Then why seperation between SPEF and SDF? confusing!!!
 

Let me repeat. SDF does not contain R&C info. But SPEF does.
 

jeevan.life said:
SPEF file has R and C values which the STA tool uses to calculate and arrive at cell and net delays and compute the crosstalk information.

SDF has annotated delays and cells are annotated with the delays. STA tool just has to annotate these delays and there is no computation involved.
Usually SDF is written out from STA tools as an input for simulation, and SPEF is read in to STA tool so that it can compute the delays.

Cheers
G1
Click to expand...

This answer explains the most. Both SDF and SPEF are generated by PnR tool, and imported to PT for timing analysis. Because SPEF contains RC info, it can be used for signal integrity check in PT SI also.
 

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