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Causes of Hold Time Violation in FPGA

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shaiko

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Hello,

Given a specific clock frequency with zero skew - large combinatorial circuits between registers can cause a Setup Time violation.

But what can cause Hold Time violations ?
 

Thanks dpaul,

But it doesn't answer my question.
From what I've seen, the examples of Hold Time Violation in the post are attributed to clock skew.

My question is:
What can cause hold time violations other than skews in the clock tree?
 

As far as I am aware, the flops within an FPGA are designed in such a way that C->Q delay is always greater than the hold time. So you cannot face hold time violations in an FPGA.
 
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    shaiko

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FPGA are designed in such a way that C->Q delay is always greater than the hold time.
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Thanks sharath666,
That's the conclusion I was coming to...

Taking it a step further and thinking ASIC (not FPGA):
A clock network has zero skew and is populated with flip-flops that have extremely fast time to output. The flip-flops are also packed very closely together so the signal propagation delay is minimal.

Is it correct to say that such a design is very prone to hold time violations?
 

Yes. Hold time violations are very common in ASICs. They are usually fixed post P&R by adding buffers in the data path so that data stays a bit longer.
 
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    shaiko

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FPGA registers, by design, would ensure that two DFFs connected from Q to D wouldn't require any extra logic to meet hold time...
Think about it, to add a buffer delay means you would have to add a LUT.

If you look at the place and route results, clock tree skew is an issue with FPGA in that the tools have to do route throughs to fix hold time problems. Xilinx even has as part of their reports the number of route throughs used.
 
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