dipin
Full Member level 4
hi,
i had designed three modules(using verilog) and make it together using a wraper.
example
module top()
::::::::::::
:::::::::::
A uut();
B uut();
c uut();
endmodule
after this, when i synthesis the top module , i need only MODULE A to get synthesized and not B and C. then next time only B not A and C
is there any way to do this.
thanks & regards
i had designed three modules(using verilog) and make it together using a wraper.
example
module top()
::::::::::::
:::::::::::
A uut();
B uut();
c uut();
endmodule
after this, when i synthesis the top module , i need only MODULE A to get synthesized and not B and C. then next time only B not A and C
is there any way to do this.
thanks & regards
Last edited: