Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Area calculation in VHDL

Status
Not open for further replies.
A

Arrowspace

Banned
Full Member level 3
Joined
Jan 23, 2015
Messages
186
Helped
3
Reputation
6
Reaction score
3
Trophy points
18
Activity points
0
Hello, How can I calculate area of design hardware in xilinx
 

Re: power calculation in VHDL

I believe what you're trying to find out is the "utilisation". This information is in the place and route (par) report or if you're using vivado you'll see it in the project window after you've synthesised or implemented the design.
 

Re: power calculation in VHDL

place and route report , I do't find area in it.

par -filter iseconfig/filter.filter -w -intstyle ise -ol high -t 1
fir_4tap_map.ncd fir_4tap.ncd fir_4tap.pcf


Constraints file: fir_4tap.pcf.
Loading device for application Rf_Device from file '3s200a.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
"fir_4tap" is an NCD, version 3.2, device xa3s200a, package ftg256, speed -4

Initializing temperature to 100.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".

Device speed data version: "PRODUCTION 1.41 2011-02-03".


Design Summary Report:

Number of External IOBs 25 out of 195 12%

Number of External Input IOBs 9

Number of External Input IBUFs 9

Number of External Output IOBs 16

Number of External Output IOBs 16

Number of External Bidir IOBs 0


Number of BUFGMUXs 1 out of 24 4%
Number of MULT18X18SIOs 1 out of 16 6%
Number of Slices 30 out of 1792 1%
Number of SLICEMs 1 out of 896 1%



Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High

Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs


Starting Placer
Total REAL time at the beginning of Placer: 10 secs
Total CPU time at the beginning of Placer: 5 secs

Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:641) REAL time: 13 secs

Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:641) REAL time: 13 secs

Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:641) REAL time: 13 secs

Phase 4.2 Initial Clock and IO Placement
.........
Phase 4.2 Initial Clock and IO Placement (Checksum:fa01a56) REAL time: 21 secs

Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:fa01a56) REAL time: 21 secs

Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:fa01a56) REAL time: 21 secs

Phase 7.3 Local Placement Optimization
..........
Phase 7.3 Local Placement Optimization (Checksum:107998ff) REAL time: 25 secs

Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:107998ff) REAL time: 25 secs

Phase 9.8 Global Placement
..
..
Phase 9.8 Global Placement (Checksum:17bbf60e) REAL time: 25 secs

Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:17bbf60e) REAL time: 25 secs

Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:17b8802e) REAL time: 26 secs

Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:17b8802e) REAL time: 26 secs

Total REAL time to Placer completion: 26 secs
Total CPU time to Placer completion: 20 secs
Writing design to file fir_4tap.ncd



Starting Router


Phase 1 : 222 unrouted; REAL time: 30 secs

Phase 2 : 170 unrouted; REAL time: 30 secs

Phase 3 : 25 unrouted; REAL time: 30 secs

Phase 4 : 25 unrouted; (Par is working to improve performance) REAL time: 30 secs

Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 30 secs

Updating file: fir_4tap.ncd with current fully routed design.

Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 31 secs

Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 31 secs

Updating file: fir_4tap.ncd with current fully routed design.

Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 34 secs

Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 34 secs

Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 34 secs

Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 34 secs

Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 34 secs

Total REAL time to Router completion: 34 secs
Total CPU time to Router completion: 26 secs

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Clk_BUFGP | BUFGMUX_X1Y0| No | 30 | 0.066 | 1.049 |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Clk | SETUP | N/A| 4.399ns| N/A| 0
_BUFGP | HOLD | 1.619ns| | 0| 0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 39 secs
Total CPU time to PAR completion: 28 secs

Peak Memory Usage: 172 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file fir_4tap.ncd



PAR done!
Click to expand...
 

Re: power calculation in VHDL

This is the resource utilization:

Number of BUFGMUXs 1 out of 24 4%
Number of MULT18X18SIOs 1 out of 16 6%
Number of Slices 30 out of 1792 1%
Number of SLICEMs 1 out of 896 1%

1 clock buffer,
1 hard IP DSP multiplier
30 slices (up to 8 FF's and 4 LUTs)
1 distributed memory.
 

With this information how can i calculate area required by my hardware ?
 

I don't know how the concept of area plays out in an FPGA. The FPGA is already manufactured. So nothing left to optimize. As far as "fitting as much logic goes into an FPGA" the above stats pointed out by ads-ee should be a good indicator to how much resources are used and how much is left.
 

Arrowspace said:
With this information how can i calculate area required by my hardware ?
Click to expand...

Since you continue to want the "area" rather than the "utilisation"...

Find the part number and package outline. Look in the datasheet to see the package dimensions. Multiply the length by the width.
 
tggzzz is talking about physical area.

Whereas add-ee and I are talking about logical utilisation.

Please mark thread as solved if one of these answers your question.
 

yes wesleytaylor , I am talking about logical area

- - - Updated - - -

I have attached IC details , how can I calculate area consume by my logic
 

Attachments

  • data.JPG
    data.JPG
    51.2 KB · Views: 113

I believe, "logical area" (not a commonly used technical term) means the actual chip area occupied by the utilized resources of your design (as listed in post #4). But why do you want this information? It's effectively meaningless for a FPGA user, only relevant for a manufacturer that wants to optimize his chip.

The area information (if you had it) neither tells much about the required chip size when implementing the logic in a different technlogy than FPGA, nor does it describe the complete area uitilization in the FPGA because routing resources aren't counted.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top