Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[moved] Synthesis RTL in synosys DC

Status
Not open for further replies.
N

njr@1

Junior Member level 2
Junior Member level 2
Joined
May 7, 2015
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
118
Dear All,

When we synthesis in Design Compiler with different clk period why does the critical path changes with the change in clock period ?
So does the area when viewing the report using report_qor.

Please help me understand this
 

When we change the clk period, the clock constraint varies. The required time for the arrival of signals from a register to another register without violations varies. So the drive strength of the cells varies. The tool will try to optimize the new constraint and will try to design accordingly. So the critical path varies. If you change the clock period, even the clock buffers and clock inverters in the clock clock tree gets changed in the new design.
 
  • Like
Reactions: njr@1

    N

    njr@1

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top