process statement in vhdl confusion

begin
process

begin 


a<='1';
a<='0';

end process;

begin
process

begin 


a<='1';

wait for 10 ns;
a<='0';

wait for 10 ns;

end process;

fsm_proc : process (clk) is
begin
  if rising_edge(clk) = '1' then
    cnt <= cnt + 1; -- default logic, if nothing else wants to change cnt, cnt will increment.
    -- cnt will not increment on this line. The intent to change cnt will be noted.
    case (state) is
    when INIT_WAIT_100MS =>
      if cnt >= SOME_VALUE then -- you can also use =, sometimes = will synthesize better, sometimes >= will.
        state <= SET_1; -- change to next state
        cnt <= 0; -- this overrides the "cnt <= cnt + 1" line.
        lcd(3 downto 0) <= "0011"; -- setting the value on the transition to the next state will mean the value is set 
        -- upon entering the state, not 1 cycle after entering the state.  This is unimportant for this design*.
      end if;
      when SET_1 =>
        -- very similar code here. 
      -- similar code for each step of the design. **
    end case;
    if rst = '1' then -- placing the reset at the end is more common in FPGA designs***
      -- where not all signals are reset.
      lcd <= (others => '0');
      cnt <= 0;
      -- other signals that need to be reset 
    end if;
  end if;
end process; -- and here is where the actual updates will occur, at the end of the process
-- and after all triggered processes have been evaluated.

process ( clock_100mhz , reset ) is 
begin
   if reset = '1' then 
      a <= '0' ;
      fsm_state <= idle ;
   elsif rising_edge ( clock_100mhz ) then	
      case fsm_state is 
         when idle =>	
            if shoot = '1' then
               a <= '1' ;
               fsm_state <= shooting ;
            end if ;					
         when shooting =>
            a <= '0' ;
            fsm_state <= idle ;		
       end case ;
   end if ;
end process ;

process
a <= '1';
wait for 10 ns;
a <= '0';
end process;

 a | a+
---+---
 x | 0

process ( A , B , C ) is
begin
C <= 
not 
( 
	( not ( A and B ) ) 
	and 
	( not ( ( not ( A and B ) ) or B ) )
) ;
end process ;

-- Given pure combinatorial logic ( no flip flops ) - notice that all signals ( a,b,c ) are in the sensitivity list.

process ( clock ) is
begin
  if rising_edge ( clock ) the
    Y <= C ;
  end if ;
end process ;

-- This Flip Flop is sensitive only to the 'clock' signal - so only this signal is in the sensitivity list.

C <= 
not 
( 
	( not ( A and B ) ) 
	and 
	( not ( ( not ( A and B ) ) or B ) )
) ;

process(clk)
begin
  if rising_edge(clk) then
    Q <= D;
  end if;
end process;