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What is the state of I/O while FPGA is in the process of configuration?
After system reset, FPGA will download the data from flash-rom(configuration). This process will take some time. In the time, What is the I/O state? "1"? "0"? or "Z"? This state will (badly) effect the peripheral IC?
Note: My PFGA is the one of Altera Cyclone Family, EP1C20F400C6.
After system reset, FPGA will download the data from flash-rom(configuration). This process will take some time. In the time, What is the I/O state? "1"? "0"? or "Z"? This state will (badly) effect the peripheral IC?
Note: My PFGA is the one of Altera Cyclone Family, EP1C20F400C6.