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Why do we have specific power up and power down sequences for ASICs

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matrixofdynamism

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ASICs and FPGAs that have a lot of power rails usually contain the sequence of power up/down as part of specification. This includes the order in which the rails should be powered up/down and also the time minimum pause between powering up/down successive rails.

Why do we need such a sequence, what are its origins?
What will happen if this sequence is not followed for power up?
What will happen if this sequence is not followed for power down?
 

We need power sequence because of the following
a) Some blocks have to start functioning before than others because of system requirements.[ this should be obvious]
b) Many times circuits are designed in such a way it will work when one of the power domains is driving the others to function properly.
c) Also from IR drop considerations and current drawn from the battery has to be kept in reasonable limit so an order is fixed.
..... this is like simple thing as in the case of a car...you close the doors before starting the ignition ;-)

if the order is not followed the results will be unknown at best and fatal at worst.
 
In some cases the requirement is due to keeping diodes from forward biasing and causing the device to "burn up". A number of FPGAs I've worked with had this issue, where one rail must be up before another power rail as some of the parasitic diodes will fail if the power is brought up in the reverse order.

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artmalik said:
..... this is like simple thing as in the case of a car...you close the doors before starting the ignition ;-)
Click to expand...
My car starts fine with the door open, but definitely won't start if the clutch isn't disengaged. My other car won't start unless the brake pedal is depressed. ;-)
 
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