Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Stuck at fault detection of a square pulse

Status
Not open for further replies.
T

tv123

Junior Member level 3
Junior Member level 3
Joined
Mar 16, 2015
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
162
Can anyboby explain how to detect stuck at faults in case of a square pulse in verilog?
 

tv123 said:
Can anyboby explain how to detect stuck at faults in case of a square pulse in verilog?
Click to expand...

What do you mean by fault in square pulse ?

Stuck at faults are detected in a physical circuit and not in a waveform. Do you mean to ask, how to detect stuck at faults in a pulse generator circuit ?
 

I would like to modify the qn as to detect the loss of a pulse
 

tv123 said:
I would like to modify the qn as to detect the loss of a pulse
Click to expand...

So you need a pulse detection circuit? Please look at this thread, maybe this is what you are looking for.

A simple google search could have easily popped this up. :)
 
  • Like
Reactions: tv123

    T

    tv123

    Points: 2
    Helpful Answer Positive Rating
The situation is like, i have an input square pulse and have to detect the situations when it is lost and become low always or may become high always.
 

tv123 said:
The situation is like, i have an input square pulse and have to detect the situations when it is lost and become low always or may become high always.
Click to expand...

If the square pulse is a clock-like signal then use a faster clock and synchronize and edge detect the synchronized version, then have a timeout counter that resets each time an edge occurs. If the timeout counter saturates (i.e. all 1's) then the counter stops at the saturation count and the stuck detection goes active.
 
  • Like
Reactions: tv123

    T

    tv123

    Points: 2
    Helpful Answer Positive Rating
The simplest solution to a missing pulse detector is a one shot that is retriggerable from the pulse itself set to the time interval expected or better, the pulse synchronized by a PLL clock which the missing pulse over +/-1/2 of the clock interval, with detection also on extra pulses a consideration.
 

ads-ee said:
If the square pulse is a clock-like signal then use a faster clock and synchronize and edge detect the synchronized version, then have a timeout counter that resets each time an edge occurs. If the timeout counter saturates (i.e. all 1's) then the counter stops at the saturation count and the stuck detection goes active.
Click to expand...

Thank you so much. I came across this. Can you suggest me any other

- - - Updated - - -

SunnySkyguy said:
The simplest solution to a missing pulse detector is a one shot that is retriggerable from the pulse itself set to the time interval expected or better, the pulse synchronized by a PLL clock which the missing pulse over +/-1/2 of the clock interval, with detection also on extra pulses a consideration.
Click to expand...

instead of using 555 can i develop it by any other means because i need modelsim simulation for that
 

You're statements in post #8 seem to contradict each other:

tv123 said:
instead of using 555 can i develop it by any other means because i need modelsim simulation for that
Click to expand...
You don't want to use a 555 and wish to use modelsim to simulate the function.

tv123 said:
Thank you so much. I came across this. Can you suggest me any other
Click to expand...
I suggested a method to perform the action without a 555 and you ask for a different suggestion?

So what do you want? You seem to already know what you want, so describe exactly what you want, instead of some vague question (post #1) with no requirements or test cases to verify functionality.
 

ads-ee said:
You're statements in post #8 seem to contradict each other:

You don't want to use a 555 and wish to use modelsim to simulate the function.


I suggested a method to perform the action without a 555 and you ask for a different suggestion?

So what do you want? You seem to already know what you want, so describe exactly what you want, instead of some vague question (post #1) with no requirements or test cases to verify functionality.
Click to expand...

Hi ads-ee, i got mixed up with the replies. i meant that i came across the approach that you described and i wanted to know whether there is any other method.
555 reply was for sunnyskyguy
 

The method I mentioned can be easily written in VHDL/Verilog and simulated in Modelsim. I've used circuits like this many times. I'm actually using one in some common library debounce code I wrote a number of years ago.
 

ads-ee said:
The method I mentioned can be easily written in VHDL/Verilog and simulated in Modelsim. I've used circuits like this many times. I'm actually using one in some common library debounce code I wrote a number of years ago.
Click to expand...

Thank you for suggesting that method, can you suggest any other
 

tv123 said:
Thank you for suggesting that method, can you suggest any other
Click to expand...

Like what? You obviously are looking for something specific, so explain why the simplest solution is inadequate for what you are doing.
 

ads-ee said:
Like what? You obviously are looking for something specific, so explain why the simplest solution is inadequate for what you are doing.
Click to expand...

i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two
 

tv123 said:
i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two
Click to expand...

Sounds like an academic research project...

I don't know of a better way to do it. I always prefer something that is easy to understand and is bug free than going with something convoluted/tricky/clever just for the sake of 1 nA power savings ;-)

If you can't use a counter then there isn't any other reliable way to determine if a given amount of time has passed with no pulse. Everything else ends up being "analog" or using digital delays in an analogish way (e.g. delay lines with LUTs).

Besides if you are doing research, then you should probably be coming up with a new method on your own (as opposed to asking someone to give you a new method). After coming up with that new method you'll have to prove it works better to convince people like me that produce fielded products.
 
  • Like
Reactions: tv123

    T

    tv123

    Points: 2
    Helpful Answer Positive Rating
  • Like
Reactions: ads-ee

    ads-ee

    ads-ee

    Points: 2
    Helpful Answer Positive Rating
tv123 said:
in terms of lesser area or power when synthesized
Click to expand...
tv123 said:
i need modelsim simulation
Click to expand...

SunnySkyguy said:
I can think of a dozen ways to make a 1 shot and have never used a 555 in 40yrs.
How about a DM74123N vintage CMOS 1 shot, with a pot set to 1% or a logic state machine... Or ....
Click to expand...
None of which will suffice in meeting the criteria set forth after a dozen posts, which are: "better" synthesis and modelsim simulation (i.e. VHDL/Verilog).

This is a good example of how a vague questions that doesn't give details of what the OP is actually looking to accomplish can run for many posts before something of substance actually comes out and also results in answers like SunnySkyguy's latest that don't match the requirements because it so darn hard to find those requirements in so many separate posts!
 

Yes original problem is vague with symptom only.

Try to give broader scope in future on post #1
Is it a metastable or missing pulse from a race condition?
Then re-sync critical path signal to master clock using FF to avoid race and missing pulse rather try to detect the fault with a shot shot.
 

I am really sorry for creating such a big confusion. I want to design a circuit to detect the attached waveform. I tried using two simultaneous counters and it is working fine. I wanted to know whether there is any other design so that i can do it in verilog hdl missing pulse.png
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top