ykishore
Member level 3
![Member level 3](/styles/images/ranks/dlevel3.gif)
What are the various SDC constraints that we need to take care of while doing clock domain crossing?
I know one is we do clock grouping as asynchronous and set_max_delay or set_max_skew. But are there any others?
Especially when we have a data bus with a valid signal crossing clocks?
I know one is we do clock grouping as asynchronous and set_max_delay or set_max_skew. But are there any others?
Especially when we have a data bus with a valid signal crossing clocks?