Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SDC constraints for clock domain crossing

Status
Not open for further replies.

ykishore

Member level 3
Member level 3
Joined
Sep 2, 2004
Messages
66
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
india
Activity points
758
What are the various SDC constraints that we need to take care of while doing clock domain crossing?

I know one is we do clock grouping as asynchronous and set_max_delay or set_max_skew. But are there any others?

Especially when we have a data bus with a valid signal crossing clocks?
 

Are you doing CDC using an STA tool? If so then doing set_clock_group would give the tool info about the asynchronous domains and it'll treat all the clock crossings as false path, which is in contrast to your intent.

Usually if its a CDC specific tool, they'll have their own guidelines to write the CDC, so you'll have to refer to their documentation to come up with an SDC.
 
I am doing CDC on FPGA. Even for ASIC, if we are doing CDC using STA tool, how do we do it? We should be indicating the crossing path as false path through clock grouping asynchronous option isnt it? or do we give some other constraints to indicate CDC in ASIC?
 
Last edited:
I am doing CDC on FPGA. Even for ASIC, if we are doing CDC using STA tool, how do we do it? We should be indicating the crossing path as false path through clock grouping asynchronous option isnt it? or do we give some other constraints to indicate CDC in ASIC?

Timing is always done for signals belonging to synchronous domains, so CDC has to be done separately with a different set of constraints.

From an STA point of view you need to tell the tool which all clocks are asynchronous so that the tool treats asynchronous clock crossing paths as false paths. Hence we usually define clock groups and set each group as asynchronous to one another.

If you are using the same STA tool for CDC, then the tool must not be made aware of the fact about which all clocks are asynchronous. So essentially we are fooling the tool into believing that all the clocks are synchronous and needs to be timed. The tool then reports paths having violations across these crossings.

Once you have the violations you'll have to manually go through the reported paths and fix them by setting false paths.

This is tedious work and needs to be reviewed thoroughly so that you don't miss out on any unmanaged crossings.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top