question regarding execution of instantiation in verilog!

I am a bit confused about the order of execution of Instantiation of modules, suppose i instantiate 5 modules one after the other ,
now will the instantiation will be done sequentially or concurrently?

What will be the behavior if

A> The instantiated modules are interdependent ?
B>The instantiated modules are independent?

There is no relation between instantiated modules. They all work independently and at the same time. It is similar to always blocks in a module.

Each module works like a chip on a circuit board - all running all the time in parrallel to one another.

Will there be any signal contention if i try to instantiate the same ipcore simultaneously from two different modules?

Indrajit Ghosh said:

Will there be any signal contention if i try to instantiate the same ipcore simultaneously from two different modules?

Click to expand...

No.
Even in a single module if you instantiate the same ip core with different instance names,there are no issues

Indrajit Ghosh said:

Will there be any signal contention if i try to instantiate the same ipcore simultaneously from two different modules?

Click to expand...

Seems to me you're thinking of an instantiated core as if it is like a subroutine in a programming language. Where you can't "call" the routine in multiple places simultaneously as the variables are shared. Keep in mind VHDL and Verilog are not software languages they are hardware description languages.

If you instantiate the ip core it is like an IC on a board if you put two of them on the board they don't share their internal circuits.

So when you learn about for loops in VHDL/Verilog, don't think they work just like for loops in software languages (as in temporal looping) they instead work like hardware (replicating spatially), e.g. you want 10 copies of a module, you can use a for loop to "generate" those copies instead of instantiating each one separately.

so basically you mean to say ,If i instantiate the same ipcore even 10 times ,it will be treated as separate piece of hardware working independtly,so even in the rtl description will it show as separate pieces of hardware?

Indrajit Ghosh said:

so basically you mean to say ,If i instantiate the same ipcore even 10 times ,it will be treated as separate piece of hardware working independtly,so even in the rtl description will it show as separate pieces of hardware?

Click to expand...

Yes,but if you are trying to use use an ip core in the same module,more than once you will have to instantiate it with different instance names.

For example,try instantiating multiple fifo's/multiple adders etc... using ip core in your code & see the schematic. You can see multiple ip cores & you will understand better

It is a horrible mistake to come at a HDL with a software mindset, it just does not work that way.

In software you are telling a processor what to DO, in a synthesizeable HDL you are telling the chip what to BE, the difference is critical to understanding what is going on.

While I am an expert C programmer I find VHDL very much easier then Verilog simply because VHDL does not mentally make me think 'C'.

Start with thinking about the hardware architecture of what you want to accomplish and go from there, far more then in (relatively trivial) software, diagrams (including timing diagrams) and data flow drawings are where design starts.

Regards, Dan.