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synthesis capture clock

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raj1435

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Hi,

Can any one explain me about capture clock time period in the synthesis timing report. To make it more clear i have the time period of the 10ns,
in the timing report i am seeing the capture clock time period is the half the total time period i.e 5ns.

can any one explain clearly why it was.

Thanks
 

It will be always half cycle path in the synthesis or full cycle. can you explain me why it will be a half cycle path.
 

If ur clock is 10 ns and if the launch is at 0ns then the capture will be at 10 ns. If you are seeing capture at 5 ns, then it must be capturing data on the negedge of clock. Otherwise you must have constrained it accordingly. Go back to the RTL and check this particular timing path.
 
Hi,

can you explain me ,what are the conditions that incorporate a half cycle time period in the RTL. from synthesis constrained point of view i havn't constrained as half cycle.
 

raj1435 said:
Hi,

can you explain me ,what are the conditions that incorporate a half cycle time period in the RTL. from synthesis constrained point of view i havn't constrained as half cycle.
Click to expand...

hi Raj1435,
it's not from what you "constraint" the path (in your design). it come from what you designed
- your launch flop L : normal, CK feed clock pin of your flop
- your capture flop C : the CK signal is inverted to original.
--> you launch data from L at rising edge of clock pin L, and then capture data at C - rising edge of clock pin C . but now, rising edge of clock pin C is from falling edge of clock pin L because of inverter in clock path between L and C. so, you have Launch at rising and Capture at falling.
that just a case, maybe you also used a paid pos-neg flops.
so, please check your logic design to see (your netlist)
 
Hi
Thanks for the reply i understand the issues. i wanted to know what is mean by paid pos-neg flops.
 

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