gstekboy
Member level 5
I had done the timing analysis of a counter in both Synopsys DC and PrimeTime, but got the same output!! Any problem ??
Design file used is counter.v
The design compiler output is attached as DC.txt
The PrimeTime output is attached as PT.txt
Design compiler output is generated by giving input as counter.v , and clock period of 2.
PrimeTime output is generated by giving input as netlist file of counter , sdf file of counter (both generated from design compiler) and clock period of 2.
View attachment DC.txt View attachment PT.txt
Design file used is counter.v
The design compiler output is attached as DC.txt
The PrimeTime output is attached as PT.txt
Design compiler output is generated by giving input as counter.v , and clock period of 2.
PrimeTime output is generated by giving input as netlist file of counter , sdf file of counter (both generated from design compiler) and clock period of 2.
View attachment DC.txt View attachment PT.txt