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Witch FPGA u r using?
is your DDR3 memory supported by core generators?
if u r using Xilinx FPGA consider these steps:
1) Start by reading datatsheet & user guide specially UG406(for Virtex6&Spartan)
2) use core generator to generate MIG Controller example design with your pin out location.
3) test example design on your board and check that there is any error or not, using error signal.
if error signals goes high your design should be checked and be debuged else be happy.
When we talk about testing of the DDR we intend to check the reads and writes to the DDR.
1.Check the interface between the FPGA and the DDR.
2.Find out how you can control the DDR through the FPGA i.e. how can you write/read from the FPGA to the DDR.
3.Perform the writes/reads and check them on the oscilloscope to confirm the working.
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