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Hello,
Please see this link https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/12-gatedelay/40-tpcg/two-phase-clock-gen_print.html
Two non-overlapping clock signals usually are made from 1 clock signal that goes through SR NOR or SR NAND latch with delay buffers in the loops, and bare in mind that S and R signals should be inverted.