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clock tree synthesis versus logic synthesis

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Logic Synthesis... is process of convertin HDL RTL code into gate level net list by synthesis tool.
(ie behavioral code into actual cirucuit doing that function)

common tools are Synopsys DC, Ambit Builgates etc..

Clock Tree synthesis is the process of inserting Clock buffers in synthesised gate level netlist..
Tools : Synopsys Astro..
Cllock Tree is required due to the heavy load(capacitance) on clock net ...

hope it helps
 
Just something to add on, it is also important to take care of clock skew in CTS, which is different in timing between registers of the same clock.
 
I think the two "sysnthesis" have not the same meaning. Clock tree synthesis means using clock tree to replace the ideal net of netlist before layout.

but logic synthesis means: 1 mapping between rtl and generic cell 2 optimization between generic cell and library cell.
 

Logic synthesis involve mapping & optimizing your RTL code to gate-level netlist.
The the P&R tools will then insert clock tree (clock tree synthesis), which consists of buffers in the gate-level netlist to balance the clock skew.
 

that totally diffrent synthesis, one is code to gate, one is net to gated-net.
 

If let your circuit must meet timing and function of timing after P&R, you have better do clock tree synthesis. It was done by CTS tool.

logic synthesis is process that translate RTL description to gate netlist.
 

logic synthesis is the flow map rtl into netlist use library. clock synthesis is inserted clock tree into placed design.
peform logic syntheis in Design-compiler or RTL compiler, otherwise, clock systhesis in PR tools, etc Astro and SOC-encounter.
 

usually logic synthesis is performed by synthesis tool, and CTS is performed by P&R tools .
 

Logic Synthesis is belong to front end flow which converts RTL code into gate level netlist, and clock tree insert is belong to layout p&r flow.
Clock Tree synthesis is the process of inserting Clock buffers in synthesised gate level netlist.
 

logic synthesis is translate --- > optimise ---- > map to sdtandard cell.

clock tree synthesis is to use a buffer tree to minimize clock skew.




carrot said:
Hi

What is the difference b/w clock tree synthesis and logic synthesis?
Click to expand...
 

eda_wiz said:
Logic Synthesis... is process of convertin HDL RTL code into gate level net list by synthesis tool.
(ie behavioral code into actual cirucuit doing that function)

common tools are Synopsys DC, Ambit Builgates etc..

Clock Tree synthesis is the process of inserting Clock buffers in synthesised gate level netlist..
Tools : Synopsys Astro..
Cllock Tree is required due to the heavy load(capacitance) on clock net ...

hope it helps
Click to expand...

Dear eda_wiz

I found your answer interesting!

Can you give me some clear idea about heavy load(capacitance) on clock net?? I mean how clock net gives rise to heavy load !!!!

Thanks in advance


sazzad
 

sazjad said:
Dear eda_wiz

I found your answer interesting!

Can you give me some clear idea about heavy load(capacitance) on clock net?? I mean how clock net gives rise to heavy load !!!!

Thanks in advance


sazzad
Click to expand...

Hi,

Clock net are heavy loaded mean..... as every individual clock net see multiple Clock input pin in devices i.e. FF . and each nets have it own capacitance to meet the timing requirement. like c-to-q delay... to meet timing one do changes like ( Insert a buffer or sometime resizing present buffer)

second point, there are multiple other factors one need to consider during CTS of SOC like power factor ( for electromigration as clock nets are ones which switches most in chip).

Rgds
 

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