Cascaded Preamplifer Design

Hi everybody,

First of all I am a newbie in RF design issues so please don't bite me for my possible stupid questions and comments :grin: Anyway, I am trying to design a low noise preamplifer for 5 GHz ISM band using Infineon LFP760 transistor. I have constructed the recommended circuit according to application note and then I modified it to satisfy the requeired S-Parameters, stabilty,noise figure etc. If I did not a cricitical mistake everything looks acceptable except for gain. Spec for gain is 30 dBm for design but according to simulation results I have around 27 dBm when I cascaded 2 stages. So my question is there any applicable strategy to increae the gain to 30 dBm without changing configuration or do I need to add a third stage? Another question in my mind arises here. How many stages can we cascade? What do I have to consider when adding extra stages or what might be the concers? By the way I am designing this amplifer in awr micr. off. and I can provide the project file in case any expert wants to browse through it.

Thanks in advance.

aguijon said:

Hi everybody,

First of all I am a newbie in RF design issues so please don't bite me for my possible stupid questions and comments :grin: Anyway, I am trying to design a low noise preamplifer for 5 GHz ISM band using Infineon LFP760 transistor. I have constructed the recommended circuit according to application note and then I modified it to satisfy the requeired S-Parameters, stabilty,noise figure etc. If I did not a cricitical mistake everything looks acceptable except for gain. Spec for gain is 30 dBm for design but according to simulation results I have around 27 dBm when I cascaded 2 stages. So my question is there any applicable strategy to increae the gain to 30 dBm without changing configuration or do I need to add a third stage? Another question in my mind arises here. How many stages can we cascade? What do I have to consider when adding extra stages or what might be the concers? By the way I am designing this amplifer in awr micr. off. and I can provide the project file in case any expert wants to browse through it.

Thanks in advance.

Click to expand...

First please correct your gain units, they should be "dB", not "dBm". dBm stands for a power related to one milliwatt (hence the "m").

Any amplifier blocks can be cascaded for a higher gain, BUT:
- pass-band filters are to be inserted between stages,
- attenuators may be needed between stages,
-careful design of DC power inputs, etc.,

all above to save amplifier stability.
In microwave radiometers and receivers, one can achieve up to 70-90 dB gain by cascading stages, but often the above must be used to get a stable amplifier.
With higher gains, noise is amplified, too, and can limit the operation of a detector if used after such amplifier. Out-of-band response and external interference can be a problem, too.

If you have obtained 27 dB instead of 30 dB Gain @ 5GHz, do not nothing !! It works fine...

If you add another amplifier stage, you will most likely end up with an oscillating amplifier chain (unless you do a REALLY great job of packaging the unit in a cutoff waveguide type housing).

Thanks to all of you for your valuable comments. Also special thanks to Jiripolivka for correcting my unit errors, I will be more careful from now on. After your comments I got some new questions in my mind. Jiripolivka, you say that adding extra amplification stages will also amplifies the noise. But according to simulation results if I use this amplifer with one stage then its noise figure is around 1.8 dB. After adding second stage noise figure becomes 1.96 dB. I mean it looks like second stage does not add too much noise as first stage and I thought this is an expected result of Frii's Formula for noise. By considering this I was not concerned about extra noise when adding a third stage. As I said I am really newbie, so maybe I am missing a crucial point. Can you clarify noise issue a little bit more please?
Biff44 you mentioned about oscillating amplifier chain that I have nearly no idea why it occurs. I know that simulation programs do not reflect the real situation exactly but how can I assure myself that my amplifer design that whether has two or more stages will not oscillate in simulator programs. Is there a practical way to predict this oscillation problem in siumalation phase?

Thanks again for your consideration.

I've used few times in my designs BFP760 (or BFP740) from Infineon. The gain of one transistor stage at 5.6GHz is about 15dB, only if use high frequency PCB material.
At lower frequencies (1.8GHz or 2.4Ghz, the gain of the transistor is much higher).
So, if you get 27dB gain using two stages and standard PCB material, don't touch anything and let things as they are.