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$setuphold syntax, verilog..

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nohj_yar

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Hello everyone..

I have some trouble of understanding the syntax $setuphold (reference_event, data_event, setup_limit, hold_limit);. I've encountered a code that looks like this

$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);

What i don't understand is the part, ",,,, CLK_dly, DI_dly".. please enlighten me..

Thanks..
 

The syntax for $setuphold according to the Veriog LRM is

$setuphold (reference_event ,data_event ,timing_check_limit ,timing_check_limit [ ,[ notifier ] [ ,[ stamptime_condition ] [ ,[ checktime_condition ] [ ,[ delayed_reference ] [ ,[ delayed_data ] ] ] ] ] ] )

So in your case reference_event will be posedge CLK, data_event will be DI, setup and hold timing check limits will be 0 time units. Giving zero will mean no violations are reported by the specify blocks, which is what is required for functional simulations. For gate-level simulations these values will be updated by the back annotated SDF.

CLK_dly and DI_dly will be the delayed events of posedge CLK and DI signals respectively.

In your module you should be using these delayed events instead of using CLK and DI directly.

For eg. if you are instantiating a standard cell (SDFF) inside the module definition

Code: 
module test (CLK, D, RST, Q);

........

SDFF (.CK(CLK_dly), .D(DI_dly),.Q(Q),.RST(RST))

specify

....

$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);

endspecify 
endmodule

For more details you can refer to the LRM https://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1620780
 
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