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ASIC design for Image processing which memory module to use

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JineshKB

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Sir,
am doing project in Image processing while doing its FPGA implementation I used the block ram resources.Now for designing ASIC in cadence encounter for the same what memory I have to use.I don't know whether IP cores are available or not in our system.How can I find whether IP cores are available (is it be a .v or .vhd file) or can I download customized memory modules from some web site.I have no idea regarding this please help.

memory reqirement : 288x384 (x 8 bits) X 2 to store 2 images
384 x (12 bits) X 16 to store intermediate values.
 

You will not find IP cores here the way you find in FPGA projects. You either have to build your own RAMs or instantiate them from some external vendor. Why don't you build your own RAMs?
 

sharath666 said:
You will not find IP cores here the way you find in FPGA projects. You either have to build your own RAMs or instantiate them from some external vendor. Why don't you build your own RAMs?
Click to expand...

Sir if I code in conventional style won't it be getting synthesized to flip flop based memory. For which the area requirement will be almost ten times than that of 6T sram cells. Then how efficient will be my design ??

Actually in my project we have made modification to an existing algorithm which would reduce power and delay (but am using more memory in my algorithm) so if I use flip flop based ram I think there won't be any power reduction.
 

The behavioural models need not be register based. You can define cells as registers in verilog and then assign them in always blocks without using clock. Furthermore, I hope you want to build this system only for simulation. You cannot do a synthesis/P&R operation as you will need the exact memory models from the memory vendor.
 
By saying "power reduction", you have to have a benchmark first to compare, correct? what is your reference design compared with which your design will have power reduction?
If you have a reference design, you need to use the same ram type that design used in order to fairly present how much power-saving your design has achieved. Otherwise, different technologies naturally provide different power consumption features. For example, you can't claim your 20nm design as better in power than an older design based on 40nm.

JineshKB said:
Sir if I code in conventional style won't it be getting synthesized to flip flop based memory. For which the area requirement will be almost ten times than that of 6T sram cells. Then how efficient will be my design ??

Actually in my project we have made modification to an existing algorithm which would reduce power and delay (but am using more memory in my algorithm) so if I use flip flop based ram I think there won't be any power reduction.
Click to expand...
 
Sir this is part of my M-tech project in stereo vision

I have 2 images from camera(am taking stereo images from vision.middlebury.edu/stereo/) and my processing is done on this images in this case if i am designing an ASIC for the same should I include the memory for storing this image in my IC or can I assume that memory storing images from camera are outside the IC which one will be proper??
 

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