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Error loading design (the design unit was not found) multi-cycle MIPS processor

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deepsetan

deepsetan

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Error loading design(the design unit was nit found) multicycle MIPS processor

Hi,does anyone know how to fix this error?. I'm trying to create multicycle processor using verilog. During the test bench simulation in modelsim, it gives

modelsim error.png
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

The tool is not able to find the design named cpu. The project window does show a file named cpu which is compiled. Check your instantiation of cpu is correct and whether the module name is correct.
 
Re: Error loading design(the design unit was nit found) multicycle MIPS processor

Check your module name in thr cpu.v file maybe you used camel case in the file. Verilog is case sensitive.
 
Re: Error loading design(the design unit was nit found) multicycle MIPS processor

sharath666 said:
The tool is not able to find the design named cpu. The project window does show a file named cpu which is compiled. Check your instantiation of cpu is correct and whether the module name is correct.
Click to expand...

Thanks a lot sharath666..but why the blue lines appearmodelsim2.png during the simulation?

- - - Updated - - -

thanks..i already fix that error..but during the simulation, why the blue lines appear?..how to correct it?modelsim2.png
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

It means that those signals are not driven. You are not driving those signals from the testbench.
 
Re: Error loading design(the design unit was nit found) multicycle MIPS processor

sharath666 said:
It means that those signals are not driven. You are not driving those signals from the testbench.
Click to expand...

what do you meant by drive those signal..i already do "force" to some of it the but it gives the flat green lines
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

If these ports are bidirectionnals, it means that they are in input mode and there are no drivers in your testbench to drive these ports.
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

Tetik said:
If these ports are bidirectionnals, it means that they are in input mode and there are no drivers in your testbench to drive these ports.
Click to expand...

Sorry for asking, but I'm really new to verilog.What do you mean by there is no drivers in the testbench?.. This is my testbench code:

module testbench;
reg clock=0;
wire[31:0] cycle, pc, inst, alu_out, mem_out;
wire regdst, alusrc, branch, memread, memwrite, regwrite, memtoreg;
wire[1:0] aluop;
wire zero;
cpu cpu1(cycle, pc, inst, alu_out, mem_out, clock,
regdst, aluop, alusrc, branch, memread,
memwrite, regwrite, memtoreg, zero);
always begin
#20 clock<=~clock;
end
initial begin
#2500 $stop;
end
initial begin
$monitor(":At Time: %d; Clk : %b; ",
$time, clock);
end
endmodule
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

You don't assign any value to the input of the module cpu. Only the clock is assigned. You have declared your wires and connected them to the cpu module but you didn't give any value to these wires.
 
Re: Error loading design(the design unit was nit found) multicycle MIPS processor

Tetik said:
You don't assign any value to the input of the module cpu. Only the clock is assigned. You have declared your wires and connected them to the cpu module but you didn't give any value to these wires.
Click to expand...

Do you mean that I've to assign some value(0 or 1) to them?..I already did "force" to some of it to assign its value..:sad::sad:
modelsim3.png
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

If they are inputs, then yes you need to assign value to them.

Usually, you drive your signals directly in your testbench not via Modelsim. I suggest you to read some tutorial on how to create a good testbench.

My verilog skills are not very good so I can't help you very much in that. Good Luck
 

Re: Error loading design(the design unit was nit found) multicycle MIPS processor

Basically you have to drive the inputs to the CPU from the external world (in this case, the testbench). Then you will observe these signals being green (either driven 0 or driven 1) instead of high Z.
If you don't drive these inputs how are you going to test the CPU. The CPU will accept these inputs, perform the required functions and then drive it's outputs.
There is no question of bidirectional signals as we are talking about a CPU block.
 

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