Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

rtl coverage issues in modelsim

Status
Not open for further replies.
A

ali_

Newbie level 3
Newbie level 3
Joined
Jan 8, 2015
Messages
3
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
30
i have made a simple fsm to detect a number which is divisible by 5. i have also written a test bench. the code is working good. Now i want to check the code coverage using following statements in modelsim

vlog -cover bcsefx tb_question_2.v question_2.v
vsim -coverage tb_question_2

modelsim is giving the code coverage for tb file but not for the rtl file. i have tried to find the code coverage for other sequential circuits i am getting code coverage for both rtl and tb files. but not in the case of fsm. am i making any mistake in making this fsm:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

module question_2 (
// Module Inputs
input         reset ,
input         x     ,
input         clk   ,
// Module Outputs
output reg    q 
);
//register declaration
reg [4:0] state_reg  ;
reg [4:0] state_next ;
 
// state parameters
localparam [4:0] S_0    = 5'b00001;
localparam [4:0] S_1    = 5'b00010;
localparam [4:0] S_2    = 5'b00100;
localparam [4:0] S_3    = 5'b01000;
localparam [4:0] S_4    = 5'b10000;
 
//state register
always @(posedge clk)
  if (reset)
    state_reg <= S_0  ;
  else
    state_reg <= state_next ;
 
 
//Next state logic  
always @*
begin
  case(state_reg)
      S_0   : if(x)
                state_next = S_1   ;
              else
                state_next = S_0   ; 
      S_1   : if(x)
                state_next = S_3   ;
              else
                state_next = S_2   ;
      S_2   : if(x)
                state_next = S_0   ;
              else
                state_next = S_4   ;
      S_3   : if(x)
                state_next = S_2   ;
              else
                state_next = S_1   ;
      S_4   : if(x)
                state_next = S_4   ;
              else
                state_next = S_3   ;
    default :   state_next = S_0   ;
  endcase
end
 
//moore type output
//input is 0 which is divisible by 5
always @(posedge clk)
  if (reset)
    q <= 1'b0;
  else 
    q <= state_reg[0];
    
endmodule
 
Last edited by a moderator:

The coding of your FSM seems to be fine. BTW, could you please tell that which Modelsim version are you using?

MSBR

- - - Updated - - -

I wrote a simple testbench for running your code:

`timescale 1ns/10ps
module tb_2;
bit reset , x, clk, q;
question_2 dut (reset,x,clk,q);
initial forever #5 clk = ~clk;
initial
begin
repeat(100)
begin
x = $random;
@ (posedge clk);
end
$stop;
end
endmodule

I used modelsim version 10.1 and found that the modelsim was showing code coverage.

May be it is the issue with your Modelsim version or something.

Thanks.
MSBR
 
i am using modelsim SE-64 10.2c, i have also used your test bench. it is still not giving any code coverage for the rtl file.
 
Well, then it seems to be a bug in Modelsim 10.2c version rather than any issue in your code. Because my test harness worked fine with your RTL code in Modelsim 10.1. If you could try some other version of Modelsim then I hope that you could be sure about that.

Thanks.
MSBR
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top