biju4u90
Full Member level 3
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This is a part of the timing report I obtained after the nanoroute stage of my design in Cadence Encounter 9.1. In order to fix the set up violations, I would like to insert buffers or upsize the cells. But how do I know which cells should I upsize or where should I insert the buffers?
Can anybody please help?? Thanx in advance
Path 1: VIOLATED Setup Check with Pin EXECUTE_INST/\acc_reg[13] /state_remap/
DFF/CK
Endpoint: EXECUTE_INST/\acc_reg[13] /state_remap/DFF/D (v) checked with
leading edge of 'm_tdsp_clk'
Beginpoint: EXECUTE_INST/\sel_op_a_reg[1] /state_remap/DFF/Q (v) triggered by
leading edge of 'm_tdsp_clk'
Path Groups: {reg2reg}
Other End Arrival Time 0.409
- Setup 0.357
+ Phase Shift 3.300
+ Cycle Adjustment 6.600
- Uncertainty 0.050
= Required Time 9.902
- Arrival Time 11.206
= Slack Time -1.304
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Timing Path:
+----------------------------------------------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required |
| | | | | | Time | Time |
|---------------------------------------------------+---------------+-------------+-------+-------+---------+----------|
| | clk ^ | | 0.000 | | 0.000 | -1.304 |
| clk__L1_I0 | A ^ -> Y v | CLKINVX20 | 0.029 | 0.027 | 0.027 | -1.277 |
| clk__L2_I0 | A v -> Y ^ | CLKINVX20 | 0.036 | 0.031 | 0.058 | -1.246 |
| EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH | CK ^ -> ECK ^ | TLATNTSCAX2 | 0.083 | 0.251 | 0.309 | -0.996 |
| EXECUTE_INST/\sel_op_a_reg[1] /state_remap/DFF | CK ^ -> Q v | SDFFRHQX1 | 0.242 | 0.381 | 0.690 | -0.615 |
| TDSP_CORE_GLUE_INST/g7976 | A v -> Y ^ | INVX1 | 0.104 | 0.130 | 0.819 | -0.485 |
| TDSP_CORE_GLUE_INST/g7940 | B ^ -> Y v | NAND2X1 | 0.098 | 0.085 | 0.905 | -0.400 |
| TDSP_CORE_GLUE_INST/g7832 | B v -> Y ^ | NOR2XL | 0.102 | 0.084 | 0.988 | -0.316 |
| TDSP_CORE_GLUE_INST/FE_OFC48_n_75 | A ^ -> Y ^ | CLKBUFX2 | 0.392 | 0.276 | 1.264 | -0.040 |
| TDSP_CORE_GLUE_INST/g7718 | A1 ^ -> Y v | AOI22X1 | 0.202 | 0.238 | 1.502 | 0.198 |
| TDSP_CORE_GLUE_INST/g7620 | A v -> Y ^ | NAND2X1 | 0.067 | 0.099 | 1.601 | 0.297 |
| TDSP_CORE_GLUE_INST/FE_OFC49_opa_0__0_ | A ^ -> Y ^ | CLKBUFX3 | 0.243 | 0.179 | 1.781 | 0.476 |
| ALU_32_INST/g1698 | A ^ -> Y v | INVX1 | 0.223 | 0.202 | 1.982 | 0.678 |
| ALU_32_INST/sub_84_22/g2782 | B v -> Y ^ | NAND2X2 | 0.090 | 0.113 | 2.096 | 0.792 |
| ALU_32_INST/sub_84_22/g2820 | A1N ^ -> Y ^ | AOI2BB1X1 | 0.106 | 0.129 | 2.225 | 0.921 |
| ALU_32_INST/sub_84_22/g2775 | CI ^ -> CO ^ | ADDFHX1 | 0.082 | 0.195 | 2.420 | 1.115 |
| ALU_32_INST/sub_84_22/g2774 | CI ^ -> CO ^ | ADDFHX1 | 0.097 | 0.195 | 2.615 | 1.310 |
| ALU_32_INST/sub_84_22/g2773 | CI ^ -> CO ^ | ADDFHX1 | 0.110 | 0.207 | 2.822 | 1.517 |
| ALU_32_INST/sub_84_22/g2772 | CI ^ -> CO ^ | ADDFHX1 | 0.105 | 0.208 | 3.030 | 1.726 |
| ALU_32_INST/sub_84_22/g2771 | B ^ -> Y v | NAND2X1 | 0.092 | 0.086 | 3.116 | 1.812 |
| ALU_32_INST/sub_84_22/g2770 | B v -> Y ^ | NAND2X1 | 0.061 | 0.062 | 3.178 | 1.873 |
| ALU_32_INST/sub_84_22/g2766 | CI ^ -> CO ^ | ADDFHX1 | 0.087 | 0.182 | 3.360 | 2.056 |
| ALU_32_INST/sub_84_22/g2765 | CI ^ -> CO ^ | ADDFHX1 | 0.090 | 0.192 | 3.553 | 2.248 |
| ALU_32_INST/sub_84_22/g2764 | CI ^ -> CO ^ | ADDFX1 | 0.069 | 0.208 | 3.761 | 2.457 |
| ALU_32_INST/sub_84_22/g2763 | A ^ -> Y v | INVX1 | 0.077 | 0.066 | 3.827 | 2.523 |
| ALU_32_INST/sub_84_22/g2762 | CI v -> CO v | ADDFHX1 | 0.166 | 0.221 | 4.048 | 2.744 |
| ALU_32_INST/sub_84_22/g2760 | CI v -> CO v | ADDFHX1 | 0.091 | 0.206 | 4.254 | 2.950 |
| ALU_32_INST/sub_84_22/g2758 | CI v -> CO v | ADDFX1 | 0.106 | 0.197 | 4.451 | 3.147 |
| ALU_32_INST/sub_84_22/g2757 | A v -> Y ^ | INVX1 | 0.049 | 0.062 | 4.514 | 3.209 |
| ALU_32_INST/sub_84_22/g2755 | CI ^ -> CO ^ | ADDFX1 | 0.099 | 0.211 | 4.725 | 3.421 |
| ALU_32_INST/sub_84_22/g2754 | CI ^ -> CO ^ | ADDFX1 | 0.090 | 0.223 | 4.948 | 3.644 |
| ALU_32_INST/sub_84_22/g2753 | CI ^ -> CO ^ | ADDFX1 | 0.130 | 0.242 | 5.190 | 3.885 |
| ALU_32_INST/sub_84_22/g2752 | CI ^ -> CO ^ | ADDFX1 | 0.112 | 0.245 | 5.435 | 4.131 |
| ALU_32_INST/sub_84_22/g2751 | CI ^ -> CO ^ | ADDFX1 | 0.095 | 0.230 | 5.665 | 4.360 |
| ALU_32_INST/sub_84_22/g2750 | CI ^ -> CO ^ | ADDFX1 | 0.132 | 0.244 | 5.909 | 4.605 |
| ALU_32_INST/sub_84_22/g2749 | CI ^ -> CO ^ | ADDFX1 | 0.093 | 0.235 | 6.144 | 4.840 |
| ALU_32_INST/sub_84_22/g2748 | CI ^ -> CO ^ | ADDFX1 | 0.101 | 0.227 | 6.371 | 5.066 |
| ALU_32_INST/sub_84_22/g2747 | CI ^ -> CO ^ | ADDFX1 | 0.070 | 0.212 | 6.583 | 5.279 |
| ALU_32_INST/sub_84_22/g2746 | A ^ -> Y v | INVX2 | 0.036 | 0.046 | 6.629 | 5.324 |
| ALU_32_INST/sub_84_22/g2745 | CI v -> CO v | ADDFX1 | 0.118 | 0.199 | 6.828 | 5.523 |
| ALU_32_INST/sub_84_22/g2743 | CI v -> CO v | ADDFX1 | 0.097 | 0.218 | 7.045 | 5.741 |
| ALU_32_INST/sub_84_22/g2742 | A v -> Y ^ | INVX1 | 0.055 | 0.063 | 7.108 | 5.804 |
| ALU_32_INST/sub_84_22/g2740 | CI ^ -> CO ^ | ADDFX1 | 0.085 | 0.206 | 7.314 | 6.009 |
| ALU_32_INST/sub_84_22/g2739 | A ^ -> Y v | INVX2 | 0.039 | 0.052 | 7.366 | 6.062 |
| ALU_32_INST/sub_84_22/g2738 | CI v -> CO v | ADDFX1 | 0.119 | 0.203 | 7.569 | 6.265 |
| ALU_32_INST/sub_84_22/g2736 | CI v -> CO v | ADDFX1 | 0.079 | 0.207 | 7.777 | 6.472 |
| ALU_32_INST/sub_84_22/g2735 | A v -> Y ^ | INVX2 | 0.033 | 0.045 | 7.821 | 6.517 |
| ALU_32_INST/sub_84_22/g2733 | CI ^ -> CO ^ | ADDFX1 | 0.094 | 0.202 | 8.024 | 6.719 |
| ALU_32_INST/sub_84_22/g2732 | CI ^ -> CO ^ | ADDFX1 | 0.094 | 0.223 | 8.247 | 6.943 |
| ALU_32_INST/sub_84_22/g2731 | CI ^ -> CO ^ | ADDFX1 | 0.098 | 0.226 | 8.473 | 7.168 |
| ALU_32_INST/sub_84_22/g2730 | CI ^ -> CO ^ | ADDFX1 | 0.142 | 0.252 | 8.724 | 7.420 |
| ALU_32_INST/sub_84_22/g2729 | B ^ -> Y v | CLKXOR2X1 | 0.061 | 0.203 | 8.927 | 7.622 |
| ALU_32_INST/sub_84_22/g2728 | B v -> Y v | XNOR2X1 | 0.060 | 0.135 | 9.061 | 7.757 |
| ALU_32_INST/g5384 | A2 v -> Y ^ | AOI32XL | 0.246 | 0.143 | 9.204 | 7.900 |
| ALU_32_INST/g5382 | B ^ -> Y v | NAND2X1 | 0.176 | 0.171 | 9.375 | 8.070 |
| ALU_32_INST/g5381 | A v -> Y ^ | INVX1 | 0.078 | 0.097 | 9.472 | 8.167 |
| ALU_32_INST/g5380 | A2 ^ -> Y v | AOI33X1 | 0.295 | 0.201 | 9.673 | 8.369 |
| ALU_32_INST/g5379 | B v -> Y ^ | NOR2BX1 | 0.357 | 0.273 | 9.946 | 8.642 |
| ALU_32_INST/g5378 | B ^ -> Y v | NAND2X1 | 0.313 | 0.275 | 10.221 | 8.917 |
| ALU_32_INST/g5377 | B v -> Y v | AND2X6 | 0.225 | 0.252 | 10.474 | 9.169 |
| ALU_32_INST/g5372 | A1 v -> Y ^ | AOI22X1 | 0.189 | 0.174 | 10.648 | 9.343 |
| ALU_32_INST/g5308 | D ^ -> Y v | NAND4X1 | 0.936 | 0.557 | 11.205 | 9.900 |
| EXECUTE_INST/\acc_reg[13] /state_remap/DFF | D v | SDFFRHQX1 | 0.936 | 0.001 | 11.206 | 9.902 |
Can anybody please help?? Thanx in advance
Path 1: VIOLATED Setup Check with Pin EXECUTE_INST/\acc_reg[13] /state_remap/
DFF/CK
Endpoint: EXECUTE_INST/\acc_reg[13] /state_remap/DFF/D (v) checked with
leading edge of 'm_tdsp_clk'
Beginpoint: EXECUTE_INST/\sel_op_a_reg[1] /state_remap/DFF/Q (v) triggered by
leading edge of 'm_tdsp_clk'
Path Groups: {reg2reg}
Other End Arrival Time 0.409
- Setup 0.357
+ Phase Shift 3.300
+ Cycle Adjustment 6.600
- Uncertainty 0.050
= Required Time 9.902
- Arrival Time 11.206
= Slack Time -1.304
Clock Rise Edge 0.000
= Beginpoint Arrival Time 0.000
Timing Path:
+----------------------------------------------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required |
| | | | | | Time | Time |
|---------------------------------------------------+---------------+-------------+-------+-------+---------+----------|
| | clk ^ | | 0.000 | | 0.000 | -1.304 |
| clk__L1_I0 | A ^ -> Y v | CLKINVX20 | 0.029 | 0.027 | 0.027 | -1.277 |
| clk__L2_I0 | A v -> Y ^ | CLKINVX20 | 0.036 | 0.031 | 0.058 | -1.246 |
| EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH | CK ^ -> ECK ^ | TLATNTSCAX2 | 0.083 | 0.251 | 0.309 | -0.996 |
| EXECUTE_INST/\sel_op_a_reg[1] /state_remap/DFF | CK ^ -> Q v | SDFFRHQX1 | 0.242 | 0.381 | 0.690 | -0.615 |
| TDSP_CORE_GLUE_INST/g7976 | A v -> Y ^ | INVX1 | 0.104 | 0.130 | 0.819 | -0.485 |
| TDSP_CORE_GLUE_INST/g7940 | B ^ -> Y v | NAND2X1 | 0.098 | 0.085 | 0.905 | -0.400 |
| TDSP_CORE_GLUE_INST/g7832 | B v -> Y ^ | NOR2XL | 0.102 | 0.084 | 0.988 | -0.316 |
| TDSP_CORE_GLUE_INST/FE_OFC48_n_75 | A ^ -> Y ^ | CLKBUFX2 | 0.392 | 0.276 | 1.264 | -0.040 |
| TDSP_CORE_GLUE_INST/g7718 | A1 ^ -> Y v | AOI22X1 | 0.202 | 0.238 | 1.502 | 0.198 |
| TDSP_CORE_GLUE_INST/g7620 | A v -> Y ^ | NAND2X1 | 0.067 | 0.099 | 1.601 | 0.297 |
| TDSP_CORE_GLUE_INST/FE_OFC49_opa_0__0_ | A ^ -> Y ^ | CLKBUFX3 | 0.243 | 0.179 | 1.781 | 0.476 |
| ALU_32_INST/g1698 | A ^ -> Y v | INVX1 | 0.223 | 0.202 | 1.982 | 0.678 |
| ALU_32_INST/sub_84_22/g2782 | B v -> Y ^ | NAND2X2 | 0.090 | 0.113 | 2.096 | 0.792 |
| ALU_32_INST/sub_84_22/g2820 | A1N ^ -> Y ^ | AOI2BB1X1 | 0.106 | 0.129 | 2.225 | 0.921 |
| ALU_32_INST/sub_84_22/g2775 | CI ^ -> CO ^ | ADDFHX1 | 0.082 | 0.195 | 2.420 | 1.115 |
| ALU_32_INST/sub_84_22/g2774 | CI ^ -> CO ^ | ADDFHX1 | 0.097 | 0.195 | 2.615 | 1.310 |
| ALU_32_INST/sub_84_22/g2773 | CI ^ -> CO ^ | ADDFHX1 | 0.110 | 0.207 | 2.822 | 1.517 |
| ALU_32_INST/sub_84_22/g2772 | CI ^ -> CO ^ | ADDFHX1 | 0.105 | 0.208 | 3.030 | 1.726 |
| ALU_32_INST/sub_84_22/g2771 | B ^ -> Y v | NAND2X1 | 0.092 | 0.086 | 3.116 | 1.812 |
| ALU_32_INST/sub_84_22/g2770 | B v -> Y ^ | NAND2X1 | 0.061 | 0.062 | 3.178 | 1.873 |
| ALU_32_INST/sub_84_22/g2766 | CI ^ -> CO ^ | ADDFHX1 | 0.087 | 0.182 | 3.360 | 2.056 |
| ALU_32_INST/sub_84_22/g2765 | CI ^ -> CO ^ | ADDFHX1 | 0.090 | 0.192 | 3.553 | 2.248 |
| ALU_32_INST/sub_84_22/g2764 | CI ^ -> CO ^ | ADDFX1 | 0.069 | 0.208 | 3.761 | 2.457 |
| ALU_32_INST/sub_84_22/g2763 | A ^ -> Y v | INVX1 | 0.077 | 0.066 | 3.827 | 2.523 |
| ALU_32_INST/sub_84_22/g2762 | CI v -> CO v | ADDFHX1 | 0.166 | 0.221 | 4.048 | 2.744 |
| ALU_32_INST/sub_84_22/g2760 | CI v -> CO v | ADDFHX1 | 0.091 | 0.206 | 4.254 | 2.950 |
| ALU_32_INST/sub_84_22/g2758 | CI v -> CO v | ADDFX1 | 0.106 | 0.197 | 4.451 | 3.147 |
| ALU_32_INST/sub_84_22/g2757 | A v -> Y ^ | INVX1 | 0.049 | 0.062 | 4.514 | 3.209 |
| ALU_32_INST/sub_84_22/g2755 | CI ^ -> CO ^ | ADDFX1 | 0.099 | 0.211 | 4.725 | 3.421 |
| ALU_32_INST/sub_84_22/g2754 | CI ^ -> CO ^ | ADDFX1 | 0.090 | 0.223 | 4.948 | 3.644 |
| ALU_32_INST/sub_84_22/g2753 | CI ^ -> CO ^ | ADDFX1 | 0.130 | 0.242 | 5.190 | 3.885 |
| ALU_32_INST/sub_84_22/g2752 | CI ^ -> CO ^ | ADDFX1 | 0.112 | 0.245 | 5.435 | 4.131 |
| ALU_32_INST/sub_84_22/g2751 | CI ^ -> CO ^ | ADDFX1 | 0.095 | 0.230 | 5.665 | 4.360 |
| ALU_32_INST/sub_84_22/g2750 | CI ^ -> CO ^ | ADDFX1 | 0.132 | 0.244 | 5.909 | 4.605 |
| ALU_32_INST/sub_84_22/g2749 | CI ^ -> CO ^ | ADDFX1 | 0.093 | 0.235 | 6.144 | 4.840 |
| ALU_32_INST/sub_84_22/g2748 | CI ^ -> CO ^ | ADDFX1 | 0.101 | 0.227 | 6.371 | 5.066 |
| ALU_32_INST/sub_84_22/g2747 | CI ^ -> CO ^ | ADDFX1 | 0.070 | 0.212 | 6.583 | 5.279 |
| ALU_32_INST/sub_84_22/g2746 | A ^ -> Y v | INVX2 | 0.036 | 0.046 | 6.629 | 5.324 |
| ALU_32_INST/sub_84_22/g2745 | CI v -> CO v | ADDFX1 | 0.118 | 0.199 | 6.828 | 5.523 |
| ALU_32_INST/sub_84_22/g2743 | CI v -> CO v | ADDFX1 | 0.097 | 0.218 | 7.045 | 5.741 |
| ALU_32_INST/sub_84_22/g2742 | A v -> Y ^ | INVX1 | 0.055 | 0.063 | 7.108 | 5.804 |
| ALU_32_INST/sub_84_22/g2740 | CI ^ -> CO ^ | ADDFX1 | 0.085 | 0.206 | 7.314 | 6.009 |
| ALU_32_INST/sub_84_22/g2739 | A ^ -> Y v | INVX2 | 0.039 | 0.052 | 7.366 | 6.062 |
| ALU_32_INST/sub_84_22/g2738 | CI v -> CO v | ADDFX1 | 0.119 | 0.203 | 7.569 | 6.265 |
| ALU_32_INST/sub_84_22/g2736 | CI v -> CO v | ADDFX1 | 0.079 | 0.207 | 7.777 | 6.472 |
| ALU_32_INST/sub_84_22/g2735 | A v -> Y ^ | INVX2 | 0.033 | 0.045 | 7.821 | 6.517 |
| ALU_32_INST/sub_84_22/g2733 | CI ^ -> CO ^ | ADDFX1 | 0.094 | 0.202 | 8.024 | 6.719 |
| ALU_32_INST/sub_84_22/g2732 | CI ^ -> CO ^ | ADDFX1 | 0.094 | 0.223 | 8.247 | 6.943 |
| ALU_32_INST/sub_84_22/g2731 | CI ^ -> CO ^ | ADDFX1 | 0.098 | 0.226 | 8.473 | 7.168 |
| ALU_32_INST/sub_84_22/g2730 | CI ^ -> CO ^ | ADDFX1 | 0.142 | 0.252 | 8.724 | 7.420 |
| ALU_32_INST/sub_84_22/g2729 | B ^ -> Y v | CLKXOR2X1 | 0.061 | 0.203 | 8.927 | 7.622 |
| ALU_32_INST/sub_84_22/g2728 | B v -> Y v | XNOR2X1 | 0.060 | 0.135 | 9.061 | 7.757 |
| ALU_32_INST/g5384 | A2 v -> Y ^ | AOI32XL | 0.246 | 0.143 | 9.204 | 7.900 |
| ALU_32_INST/g5382 | B ^ -> Y v | NAND2X1 | 0.176 | 0.171 | 9.375 | 8.070 |
| ALU_32_INST/g5381 | A v -> Y ^ | INVX1 | 0.078 | 0.097 | 9.472 | 8.167 |
| ALU_32_INST/g5380 | A2 ^ -> Y v | AOI33X1 | 0.295 | 0.201 | 9.673 | 8.369 |
| ALU_32_INST/g5379 | B v -> Y ^ | NOR2BX1 | 0.357 | 0.273 | 9.946 | 8.642 |
| ALU_32_INST/g5378 | B ^ -> Y v | NAND2X1 | 0.313 | 0.275 | 10.221 | 8.917 |
| ALU_32_INST/g5377 | B v -> Y v | AND2X6 | 0.225 | 0.252 | 10.474 | 9.169 |
| ALU_32_INST/g5372 | A1 v -> Y ^ | AOI22X1 | 0.189 | 0.174 | 10.648 | 9.343 |
| ALU_32_INST/g5308 | D ^ -> Y v | NAND4X1 | 0.936 | 0.557 | 11.205 | 9.900 |
| EXECUTE_INST/\acc_reg[13] /state_remap/DFF | D v | SDFFRHQX1 | 0.936 | 0.001 | 11.206 | 9.902 |