aelbad
Junior Member level 1
Hi all,
can I implement a wrapper which basically only assign all the inputs and outputs to 0 around my already synthesized block using verilog RTL code and synthesis that code into a wrapper around my already synthesized block?:thinker:
Thank you,
Cheers,
can I implement a wrapper which basically only assign all the inputs and outputs to 0 around my already synthesized block using verilog RTL code and synthesis that code into a wrapper around my already synthesized block?:thinker:
Thank you,
Cheers,