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ADC interface with FPGA

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Sweta25

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Hi everyone,
I am just a beginner and i wish to interface an adc ( Pmod AD5) with an fpga (spartan 6). I am unable to come up with the correct VHDL codes. The datasheet to refer to is the AD7193. Can anyone help?? any help would be highly appreciated... Thanks :D
 

Hi Sweta,

I would suggest, you go through the ADC data sheet, the Pmod AD5 supports SPI interface, so you need to study this interface ( if you are not familiar with). You need to understand the requirement of this IC, its control signals and timing diagram.
accordingly you need to design the IO port and implement the logic. considering all this, you can start with some VHDL code, if you find any problem then you can post it and I am sure there are many people who will help you on this.

Good luck.
 
Hi,
I used the clock divider to set the clock of the ADC (according to dataheet 4.8kHz)... I will input an analog signal to the ADC...problem is how to check for the end of the conversion to digital so that i can send it to the FPGA??
Thanks
 

I used the clock divider to set the clock of the ADC (according to dataheet 4.8kHz)
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4.8 kHz is the maximum sampling rate, not the clock frequency. The ADC clock frequency is generated by a crystal on the module. You'll generate a SPI interface timing according to the datasheet specification. Maximum SCLK frequency is 5 MHz, 1 or 2 MHz could be a good starting point.

Because SPI operation involves actions at both SCLK edges, the SPI interface will be usually controlled by a clock enable of half the SCLK frequency, generated by dividing the design clock.
 
Thanks...one doubt cleared...I read that when Dout/RDY is low , conversion is complete...I thought the pin Dout will give me the digital output :/
 

I read that when Dout/RDY is low , conversion is complete...I thought the pin Dout will give me the digital output
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Dout is the data output, RDY function is dual-use for your ease. You can also determine end of conversion by reading a status register, I presume.
 
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From the datasheet, in order to have continuous reading, the AD7193 must be configured, what type of configuration is required?? and it also says that sufficient SCLK must be applied to ADC, what number of cycles are required?? I know I am being really annoying with my questions but i really need to do this...THANKS :)
 

Sweta25 said:
From the datasheet, in order to have continuous reading, the AD7193 must be configured, what type of configuration is required?? and it also says that sufficient SCLK must be applied to ADC, what number of cycles are required?? I know I am being really annoying with my questions but i really need to do this...THANKS :)
Click to expand...

Is reading a 56 page datasheet that hard to do? Looking at the TOC pages 21-30 has the information you need to program the configuration registers.

I suggest you take an hour and read the 56 pages from front to back twice. First time just read the whole datasheet. Second time read it and mark things that don't seem to make any sense to you. Then you could ask targeted questions pointing out the page and paragraph (or even post a screen shot of the section).
 
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