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optimum design: FIFO or shift register

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childs72

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I have a design where I need to pick up 8-b data at exactly 4 cycles later. Thus I have following options:
1. Use FIFO of depth 4.
2. Use 4*8-b shift registers.

Both are able to serve the purpose of my design, but I wonder which will be better solution in terms of resource, timing & power? Opinions on other design perspective (such as flexibility for ECO) are welcomed as well! Thanks!
 

Just to clarify your assumption: you have each clock cycle a 8b data, and you want to used these data 4 clock cycles later:
input a@1;b@2;c@3;d@4;e@5;... (@clock cycle number)
output -@1;-@2;-@3;-@4;a@5;b@6;....

Well, how your FIFO will be implemented? I imagine as 4*8bits.
The question is more do you have a mux 4to1 to select the 8bit data to read or you want to move the data from one bank to another bank (worst power)?
 
rca said:
Just to clarify your assumption: you have each clock cycle a 8b data, and you want to used these data 4 clock cycles later:
input a@1;b@2;c@3;d@4;e@5;... (@clock cycle number)
output -@1;-@2;-@3;-@4;a@5;b@6;....

Well, how your FIFO will be implemented? I imagine as 4*8bits.
The question is more do you have a mux 4to1 to select the 8bit data to read or you want to move the data from one bank to another bank (worst power)?
Click to expand...

Hi rca,

To implement as FIFO, I shall code it "as proper FIFO"... which comes with read-enable, write-enable, full & empty flag. Read & write pointer will be pointing to registers which will be read/write and yes it shall be 4*8-b FIFO

Meanwhile, when you mentioned "to move the data from one bank to another bank", do you mean shift register implementation (sounds to me you do, correct me if I am wrong)?

So do you mean if data is coming in every clock cycle, shift registers will consume more power compared to FIFO? (after you mentioned, this sounds pretty correct)

Thanks.
 

childs72 said:
So do you mean if data is coming in every clock cycle, shift registers will consume more power compared to FIFO? (after you mentioned, this sounds pretty correct)
Thanks.
Click to expand...
Definitely consumes more power as all the bits in all the registers could change every clock cycle, in the case of a proper FIFO only those registers that are being updated will change and the registers managing the pointers.

I would go so far as to say you don't need the read and write enables along with the flags. Just fix the FIFO to have a offset in the read and write addresses and go from there. Thinking about it you probably don't even need to have different addresses they should be the same:
Code: 
idx: 0 1 2 3 0 1 2 3 0
wr:  0 1 2 3 4 5 6 7 8
rd:          0 1 2 3 4 5 6 7 8
As they are registers (not memory) you can read the old value and load the new value at the same time.
 
Hi, This is my opinions:
Area: Shift register is better, it doesn't read/write pointer
Timing: Shift register is better, there isn't any combitional logic
Power: Not sure, even though shift register maybe have a lot of change on bits, but FIFO has more area to implement address&mux, that will bring more static/dynamic power.
correct me if i'm wrong. Thanks
 
Thanks guys, rca provided a pretty good high level view, ads-ee gave a good alternative solution, and yanshangzhao added the remaining pieces...

As to round-up in general, I think:
- Shift register pros: less area, better timing
- FIFO pros: less power (esp when register-depth gets huge) since not all registers are updated every clock cycle

Also, FIFO higher area cost can be reduced if we code it the way that ignore unnecessary function (for example, separated read & write pointer, full & empty flag)
 

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