sharath666
Advanced Member level 2
1.Why is the full and the empty high initially?
2.Why are you getting dataout as 0 for first 2 reads?
2.Why are you getting dataout as 0 for first 2 reads?
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1.Why is the full and the empty high initially?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_misc.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity fifo_5r is
port( reset: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
wr_en1: out std_logic;
rd_en1: out std_logic;
din: out std_logic_vector(31 downto 0);
dataout: out std_logic_vector(127 downto 0);
full: out std_logic;
almost_full: out std_logic;
empty: out std_logic;
almost_empty: out std_logic;
rd_data_count: out std_logic_vector(8 downto 0);
wr_data_count: out std_logic_vector(10 downto 0);
prog_full: out std_logic;
prog_empty: out std_logic
);
end fifo_5r;
architecture Behavioral of fifo_5r is
signal dout: std_logic_vector(127 downto 0);
signal count : std_logic_vector(31 downto 0 );
signal wr_en : std_logic;
signal rd_en : std_logic;
type state_type is (rst1,write1,write2,write3,write4,write5,read1);
signal state : state_type;
component fifo_generator_v6_2
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(31 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(127 downto 0);
full: out std_logic;
almost_full: out std_logic;
empty: out std_logic;
almost_empty: out std_logic;
rd_data_count: out std_logic_vector(8 downto 0);
wr_data_count: out std_logic_vector(10 downto 0);
prog_full: out std_logic;
prog_empty: out std_logic);
end component;
begin
wr_en1<=wr_en;
rd_en1<=rd_en;
din<=count;
process(wr_clk,reset)
begin
if(wr_clk'event and wr_clk='1') then
if(reset ='1') then
count <= (others=>'0');
elsif(wr_en= '1') then
count<= count + 1;
end if;
end if;
end process;
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
wr_en<= '0';
rd_en<='0';
state<= write1;
else
case (state) is
when rst1=>
state<=write1;
when write1=>
wr_en<='1';
rd_en<='0';
state<=write2;
when write2=>
wr_en<='1';
rd_en<='0';
state<=write3;
when write3=>
wr_en<='1';
rd_en<='0';
state<=write4;
when write4=>
wr_en<='1';
rd_en<='0';
state<=write5;
when write5=>
wr_en<='1';
rd_en<='0';
state<=read1;
when read1=>
wr_en<='0';
rd_en<='1';
state<=write1;
when others=>
state <= rst1;
end case;
end if;
end if;
end process;
U0 : fifo_generator_v6_2
port map (
rst => reset,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => count,
wr_en => wr_en,
rd_en => rd_en,
dout => dataout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty
);
end Behavioral;
i think for the first 2 reads, dataout is 0 is bcz of delay since we are reading the 5 writes at a same time,, actually i dont have original simulation i just simulated it on my own,it still wasnt approved by my sir completly , its embarassing but i cnt do anything:-?.
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
wr_en<= '0';
rd_en<='0';
else
state<= write1;
case (state) is
when rst1=>
state<=write1;
when write1=>
wr_en<='1';
rd_en<='0';
state<=write2;
when write2=>
wr_en<='1';
rd_en<='0';
state<=write3;
when write3=>
wr_en<='1';
rd_en<='0';
state<=write4;
when write4=>
wr_en<='1';
rd_en<='0';
state<=write5;
when write5=>
wr_en<='1';
rd_en<='0';
state<=read1;
when others=>
state <= rst1;
end case;
end if;
end if;
end process;
process(rd_clk)
begin
if(rd_clk'event and rd_clk='1') then
if (reset='1') then
wr_en<= '0';
rd_en<='0';
else
state2<= read1;
case (state2) is
when rst1=>
state2<=read1;
when read1=>
wr_en<='0';
rd_en<='1';
state2<=write1;
when others=>
state2 <= rst1;
end case;
end if;
end if;
end process;
Involving the "little" problem that wr_en and rd_en can be only assigned in one or the other process, but not in both. Reconsider!I wrote using 2 clock processes
! sir it is said that to not to "generate wr_en and rd_en in the same process block. rd_en should be generated on rd_clk and not on wr_clk. Have a different process block for that." ???? so i did like that .
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
[COLOR="#00FF00"]wr_en<= '0';[/COLOR]
[COLOR="#FF0000"]rd_en<='0';[/COLOR]
else
state<= write1;
case (state) is
A signal can be generated ONLY in 1 block. wr_en using wr_clk and rd_en using rd_clk and in different process blocks.
You have not added reset to the sensitivity list either.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_misc.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity fifo_5r is
port( reset: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
wr_en1: out std_logic;
rd_en1: out std_logic;
din: out std_logic_vector(31 downto 0);
dataout: out std_logic_vector(127 downto 0);
full: out std_logic;
almost_full: out std_logic;
empty: out std_logic;
almost_empty: out std_logic;
rd_data_count: out std_logic_vector(8 downto 0);
wr_data_count: out std_logic_vector(10 downto 0);
prog_full: out std_logic;
prog_empty: out std_logic
);
end fifo_5r;
architecture Behavioral of fifo_5r is
signal dout: std_logic_vector(127 downto 0);
signal count : std_logic_vector(31 downto 0 );
signal wr_en : std_logic;
signal rd_en : std_logic;
type state_type is (rst1,write1,write2,write3,write4,write5,read1);
signal state,state2 : state_type;
component fifo_generator_v6_2
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(31 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(127 downto 0);
full: out std_logic;
almost_full: out std_logic;
empty: out std_logic;
almost_empty: out std_logic;
rd_data_count: out std_logic_vector(8 downto 0);
wr_data_count: out std_logic_vector(10 downto 0);
prog_full: out std_logic;
prog_empty: out std_logic);
end component;
begin
wr_en1<=wr_en;
rd_en1<=rd_en;
din<=count;
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if(reset ='1') then
count <= (others=>'0');
elsif(wr_en= '1') then
count<= count + 1;
end if;
end if;
end process;
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
wr_en<= '0';
else
state<= write1;
case (state) is
when rst1=>
state<=write1;
when write1=>
wr_en<='1';
state<=write2;
when write2=>
wr_en<='1';
state<=write3;
when write3=>
wr_en<='1';
state<=write4;
when write4=>
wr_en<='1';
state<=read1;
when others=>
state <= rst1;
end case;
end if;
end if;
end process;
process(rd_clk)
begin
if(rd_clk'event and rd_clk='1') then
if (reset='1') then
rd_en<='0';
else
state2<= read1;
case (state2) is
when rst1=>
state2<=read1;
when read1=>
rd_en<='1';
state2<=write1;
when others=>
state2 <= rst1;
end case;
end if;
end if;
end process;
U0 : fifo_generator_v6_2
port map (
rst => reset,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => count,
wr_en => wr_en,
rd_en => rd_en,
dout => dataout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty
);
end Behavioral;
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
wr_en<= '0';
state<=write1;
else
case (state) is
when rst1=>
state<=write1;
when write1=>
wr_en<='1';
state<=write2;
when write2=>
wr_en<='1';
state<=write3;
when write3=>
wr_en<='1';
state<=write4;
when write4=>
wr_en<='1';
state<=read1;
when others=>
state <= rst1;
end case;
end if;
end if;
end process;
process(rd_clk)
begin
if(rd_clk'event and rd_clk='1') then
if (reset='1') then
rd_en<='0';
state2<=read1;
else
case (state2) is
when rst1=>
state2<=read1;
when read1=>
rd_en<='1';
state2<=write1;
when others=>
state2 <= rst1;
end case;
end if;
end if;
end process;
process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
if (reset='1') then
wr_en<= '0';
state<=write1;
else
case (state) is
when rst1=>
wr_en<='0';
state<=write1;
when write1=>
wr_en<='1';
state<=write2;
when write2=>
wr_en<='1';
state<=write3;
when write3=>
wr_en<='1';
state<=write4;
when write4=>
wr_en<='1';
state<=write5;
when write5=>
wr_en<='1';
state<=read1;
when others=>
state <= rst1;
end case;
end if;
end if;
end process;
process(rd_clk)
begin
if(rd_clk'event and rd_clk='1') then
if (reset='1') then
rd_en<='0';
state<=read1;
else
case (state2) is
when rst1=>
rd_en<='0';
state2<=read1;
when read1=>
rd_en<='1';
state2<=write1;
when others=>
state2 <= rst1;
end case;
end if;
end if;
end process;
1. You were told to use a width changing FIFO (32 -> 5*32) in posts #2 & #4 (which was wrong, I'll get back to that).sandy3129 said:hai every one , my question is , normally in a fifo we write into the fifo and then read it from the fifo in the next cycle, so datacount will be '1', but what if i want to write 5 data serially and then read it from fifo , i want dataout to be read as 5 bunches at a time . here is my code
when write5=>
wr_en<='1';
state<=read1;
FIFO writing:
w1, w2, w3, w4, w5, w6, w7, w8, w9, w10
FIFO reading from your 32-to-128 FIFO
w1,w2,w3,w4 = first word read
w5,w6,w7,w8 = second word read
w9,w10.... = third word read
according to what you are trying to do you want to read:
w1,w2,w3,w4,w5 = first word read (5 write words)
w6,w7,w8,w9,w10 = second word read (5 more write words)