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For VHDL NOT is an inversion operation, but in Verilog, which is what the OP wants, the logical operation is ! and the bitwise operator is ~.Not is a miscellaneous or logical operator .
Get a text editor and start using it to write code rather than posting clueless posts.jus gimme an idea how to write d code
genvar i;
generate
for( i=0; i<length; i=i+1 )
begin :
if somevariable_bitposition
assign working = not working;
else
assign working = working;
endif
end
endgenerate
The rest of my post is obviously included in the cut & paste to Ali-express……