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Verilog RAM initialization

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riky126

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Hi everybody, this is my first post in this forum and i need your help :)

I need to initialize different istances of the same verilog module RAM.v from a single data file for all instances (e.g. if i had 16 istances of RAM.v each with 10 WORD of 6 bit, then my data file consists of 10*16 lines of binary data).

I can't use readmemb because it addresses RAM to be initialized, not the data file.
I think i need something to choose read file start point and offset in order to initialize each RAM with different part of the data file. Is it possible?

P:S. Sorry for my bad english!
 

Two options I see:

For smaller RAMs, read the entire file into one big memory, then copy a slice of the memory into your RAMs. SystemVerilog makes this easy because you can copy slices of memories in a single assignment.

For larger memories, use $fscanf to read one word at a time, and store it in the appropriate memory.
 
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