dnanar
Junior Member level 1
Hi,
I'm looking for a way to convert a Behavorial description (in VHDL or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys.
I've tried to look into Design Compiler / Nanosim but I couldn't find anyway of doing that. Is there any other software to do this please? Or did I miss something with these tools?
Thanks.
I'm looking for a way to convert a Behavorial description (in VHDL or VERILOG) into a (H)SPICE netlist. I did it in the past with tools from Cadence, but in my current situation I can only use tools from Synopsys.
I've tried to look into Design Compiler / Nanosim but I couldn't find anyway of doing that. Is there any other software to do this please? Or did I miss something with these tools?
Thanks.