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Verilog HDL for clock frequency divider

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amerah

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I need Verilog HDL to Design a digital component that receives a main clock signal (clk) and generates four other clock signals out of it: clk8, clk16, clk32, and clk64. The frequency of these clocks is the division of the frequency of the original clock by 8, 16, 32, and 64, respectively. The circuit also has an active-low reset signal.
Can anyone help me ???
 

Hi, there are many ways of implenting it.
One method is - you can use a variable that counts the input signal. For example when that count reaches 2, invert the output..and you are going to get divide by 2 clk...
 
gs65 said:
Hi, there are many ways of implenting it.
One method is - you can use a variable that counts the input signal. For example when that count reaches 2, invert the output..and you are going to get divide by 2 clk...
Click to expand...

I know the idea but i want the code for it plz help me
??
 

If you know the "idea" then open a text editor and start typing the Verilog.

I can hardly believe the sense of entitlement that some posters think they have requesting code from volunteers....
DO YOUR OWN WORK.
Post when you can figure out what is wrong with the work you did.
 

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