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A few questions about Verilog

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shaiko

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Hello,

1. Does Verilog support 3D arrays?
2. Does Verilog support unconstrained ports in module declaration?
3. What is the Verilog equivalent to a VHDL generic?
4. What is the Verilog equivalent to a VHDL generic?
 

Any number of array dimensions may be declared. Arrays of nets were
added in Verilog-2001.
FYR -


Does Verilog support unconstrained ports in module declaration?
I dnt know , looking for someone to answer.

The generate in this context is optional as a for loop outside procedural will be interpreted as generate for.

Parmeter is equivalent of genric in verilog
 
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    shaiko

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Any number of array dimensions may be declared.
Click to expand...
But would it synthesize?

Arrays of nets were added in Verilog-2001.
Click to expand...
I know about "wire" & "reg"...but what is a Verilog net ?
 

Mulitdimensional arrays are synthesizable (note I did not use it to infer RAM).

Wire and reg are Verilog net types. There aren't that many types in Verilog but there are some.

In sythesizable Verilog I've never heard of unconstrained ports. If it exists I would check the SV additions. I haven't gone thru the entire LRM, as I can't use any of the SV features, due to lack of tool support.
 
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    shaiko

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@ ads-ee
as of my knowledge multi dimensional arrays are not synthesizable.. i tried it .. i did not get... if i am wrong , can u suggest me an example which is synthesizable.
 

gs65 said:
@ ads-ee
as of my knowledge multi dimensional arrays are not synthesizable.. i tried it .. i did not get... if i am wrong , can u suggest me an example which is synthesizable.
Click to expand...

I doubt this statement somewhat, as the small amount of verilog Ive done (though it was SV) had a 2d array of signed and unsigned values in several ports. It synthesised just fine in Quartus.
 

TrickyDicky,

What about unconstrained ports (single or multidimensional )?
 

Normal verilog does not support open arrays on ports. System verilog does.
 
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    shaiko

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Reviewing this thread is somehow frustrating. All questions that have been asked are answered in the Verilog and System Verilog LRM. Regarding synthesis, you can either refer to IEEE 1364.1 or in most cases apply common sense:

What kind of reasons hinders a language feature to be synthesized?
If it can't be represented in actual hardware.
Think again!
 

I was about to post a similar point - it sounds like you're annoyed you cant do what you wanted in your other threads in VHDL, so now you're considering verilog.

If you're fighting the language, you're probably doing it wrong.
 

refer to IEEE 1364.1 or in most cases apply common sense:

What kind of reasons hinders a language feature to be synthesized?
If it can't be represented in actual hardware.
Think again!
Click to expand...

I don't see how N sized arrays and ports that get constrained according to the signal that drives them defies common sense.

it sounds like you're annoyed you cant do what you wanted in your other threads in VHDL, so now you're considering Verilog.
Click to expand...
Not at all. I'm not on a search for alternatives to VHDL...just trying to educate myself about the differences between both HDLs.

If you're fighting the language, you're probably doing it wrong.
Click to expand...
I disagree with this statement. Would you say the same thing about VHDL 1987 ?
Designers "fought" with that standard and that what lead to superseding standards.
 

Verilog allows stuff like this and it will synthesize. I've used it, but can't provide the code as it was done for a previous job.
Code: 
wire [15:0] mult_dim_sig [0:7] [0:31];

The reason for doing something like this is when I've used generates that are connecting up multiple things that are naturally array like. So instead of some ugly unreadable code like:

Code: 
wire [32*8*16-1:0] mult_dim_sig;
mult_dim_sig[16*(32*j+i) +:16] //This is probably not even indexing correctly, which is why I don't do this.

//I instead just code this (i:0-7, j:0-31)
mult_dim_sig[i][j]

//And if I just want a slice:
mult_dim_sig[i][j][11:8]
 

No vendor ever claimed to support IEEE 1364.1. From my perspective, anything you can compile and execute in simulation can be synthesized. It's just a simple matter of programming, time and money.

SystemVerilog has dynamic arrays and parametrized functions that gives you similar functionality to an unconstrained array in VHDL. There is no reason these can't be synthesized with the proper constraints, but as far as I know, no synthesis tool does.
 

shaiko said:
I disagree with this statement. Would you say the same thing about VHDL 1987 ?
Designers "fought" with that standard and that what lead to superseding standards.
Click to expand...

Some fought, while the majority stuck with it and made money.
For a design that needs to be made, fighting against the language and tools is a silly idea.
By all means, make enhancement requests, use cases and try and get the language "improved", but in the mean time, you need to make do or you go bankrupt
 

No vendor ever claimed to support IEEE 1364.1. From my perspective, anything you can compile and execute in simulation can be synthesized. It's just a simple matter of programming, time and money.
Click to expand...

Although not explicitely supported, 1364.1 chapter 5 (modelling hardware elements) is the only vendor independent specification of the synthesis syntax for synchronous hardware (clocked registers). I don't know if the syntax has been originally implemented by Synopsys or another tool company, but it has been adopted as a de-facto standard.

Apart from the hardware modelling point, I agree with "anything you can compile and execute in simulation".

There's no reason why e.g. multi-dimensional arrays that are defined in the LRM shouldn't be compilable to hardware, except for limitations in the language support of a specific tool.
 

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