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[SOLVED] Signed multiplier in Verilog. "signed" doesn't work

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oak_tree

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Hi,

I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me.
Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea?

The code:
========
Code Verilog - [expand]
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module mult (one_a, dccfltro, multout);
 
input         [7:0]    one_a; 
input  signed [13:0]   dccfltro;
output signed [22:0]   multout;
 
wire signed  [22:0]   multout;
 
// one_a is unsigned, so treat is as positive
assign multout = dccfltro * {1'b0, one_a};
 
endmodule
 
Testbench:
=======
module mult_tb1 ();
 
wire signed [22:0] multout;
 
mult mult (
        .dccfltro (14'h2000),
        .one_a    (8'hff),
        .multout  (multout)
    ); 
 
endmodule
 
Last edited by a moderator:

oak_tree said:
Hi,

I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me.
Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea?

The code:
========
Code Verilog - [expand]
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module mult (one_a, dccfltro, multout);
 
input         [7:0]    one_a; 
input  signed [13:0]   dccfltro;
output signed [22:0]   multout;
 
wire signed  [22:0]   multout;
 
// one_a is unsigned, so treat is as positive
assign multout = dccfltro * {1'b0, one_a};
 
endmodule
 
Testbench:
=======
module mult_tb1 ();
 
wire signed [22:0] multout;
 
mult mult (
        .dccfltro (14'h2000),
        .one_a    (8'hff),
        .multout  (multout)
    ); 
 
endmodule
Click to expand...
Hi

A bit rusty but I think there is something missing-you have an error in the logic design? Maybe this helps
**broken link removed**
 

oak_tree said:
Hi,

I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me.
Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea?
Code Verilog - [expand]
1
2
3
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7
8

input         [7:0]    one_a; 
input  signed [13:0]   dccfltro;
output signed [22:0]   multout;
 
wire signed  [22:0]   multout;
 
// one_a is unsigned, so treat is as positive
assign multout = dccfltro * {1'b0, one_a};
Click to expand...
All inputs to the * have to be signed for Verilog to produce signed values for a result. Define your one_a as input signed [8:0] one_a;

https://billauer.co.il/blog/2012/10/signed-arithmetics-verilog/
 
Last edited:
0x1FE000 is the correct answer for what you have done.

In Verilog, the sign of an assignment is determined solely by the right hand side of the equation. In your case you have a signed value multiplied with an unsigned value. The result of (signed * unsigned) is unsigned. All operands must be signed to get a signed result.

r.b.

Ooops, missed the previous replies!
 
Last edited:
Thanks for the replies. I had 'signed' also for one_a. However, what prevented it from working is {1'b0, one_a} (the 0 in front).

What I did after reading the replies is define one_a as "signed [8:0]", and then drove 0 for the MSB in the instantiation. That works.

Thanks again for all the replies!
 

oak_tree said:
Hi,

I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me.
Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea?

The code:
========
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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26

module mult (one_a, dccfltro, multout);
 
input         [7:0]    one_a; 
input  signed [13:0]   dccfltro;
output signed [22:0]   multout;
 
wire signed  [22:0]   multout;
 
// one_a is unsigned, so treat is as positive
assign multout = dccfltro * $signed{1'b0, one_a};
 
endmodule
 
Testbench:
=======
module mult_tb1 ();
 
wire signed [22:0] multout;
 
mult mult (
        .dccfltro (14'h2000),
        .one_a    (8'hff),
        .multout  (multout)
    ); 
 
endmodule
Click to expand...


I think this will also work,
in this case you can keep the one_a as unsigned.
 
Re: Signed multiplier in Verilog. "signed" doesn't work

Thanks Shibin.

It worked, but I needed to add () in order not to get a compliation error:

Code: 
assign multout = dccfltro * $signed ({1'b0, one_a});
 
Last edited by a moderator:

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