dpaul
Advanced Member level 5
Hello all,
We are looking for CISC(x86) and RISC uP cores to be used in university research projects. We can also pay licensing fees upto a certain amount (which is of course not a significant amount).
We should be able to implement this core in an FPGA(pref. Xilinx) with the availability of popular i/f (USB/JTAG/etc) and then use some popular tool-chains.
Main target is to do some RTL level h/w changes and then work on tweaking the instruction set and work @compiler level.
What options are out there OTHER THAN the ones @OpenCores, Leon3 SPARC dev platform and the one through the ARM Uni Program (ARM Cortex-M0 DesignStart Processor)?
Please share your comments, suggestions and experiences.
Thanks.
We are looking for CISC(x86) and RISC uP cores to be used in university research projects. We can also pay licensing fees upto a certain amount (which is of course not a significant amount).
We should be able to implement this core in an FPGA(pref. Xilinx) with the availability of popular i/f (USB/JTAG/etc) and then use some popular tool-chains.
Main target is to do some RTL level h/w changes and then work on tweaking the instruction set and work @compiler level.
What options are out there OTHER THAN the ones @OpenCores, Leon3 SPARC dev platform and the one through the ARM Uni Program (ARM Cortex-M0 DesignStart Processor)?
Please share your comments, suggestions and experiences.
Thanks.
