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rising and falling time matching

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william_luo

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Hi, all

I have a question about transistors matching. For inverter, I know that the width ratio of pmos to nmos is nearly 2:1 (tsmc18) for getting equal rising and falling time. I just wonder, for other circuits, like NAND2 or XOR2, do I need to match transistors for worst case? (like NAND2 shown below, in this case, )

When I took this course in class, the lab tutorial just told me that for two input cases (NAND2 or XOR2), give one input VDD, change other input signal. But obviously, this is not the worst case. Can someone explain this for me? Thank you in advance.

Regards,
 

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william_luo said:
Hi, all

I have a question about transistors matching. For inverter, I know that the width ratio of pmos to nmos is nearly 2:1 (tsmc18) for getting equal rising and falling time. I just wonder, for other circuits, like NAND2 or XOR2, do I need to match transistors for worst case? (like NAND2 shown below, in this case, )

Regards,
Click to expand...

If it is really needed to match the rising and falling time of the nand2 gate (as an example) under all conditions , then we use symmetric gate type and then size the NMOS and PMOS properly.


nand_symmetric.png


Use this type of symmetric structure and then size the gates.
 

Thanks for your reply.
But I just wonder in which cases do I need to match the rising and falling time under worst case (or other conditions), or generally the matching work in the condition of giving one input VDD (NAND2) is enough?
 

The above mentioned type of symmetric nand gate will provide you equal rise and fall time in all the cases. The price you need to pay for this is higher no. of transistors.
Either this equal rise and fall time is required or not depends upon your requirement. Usually this is a rare requirement I believe.
 
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