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Basic difference between RC and DC

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limitless_21

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Hi all,

There are 2 synthesis tools which are being used in our industry commonly i.e RC (RTL Compiler - Cadence) and DC (Design Compiler - Synopsys).
I wanted to know what is the basic difference between them or what all differs when we run the two tools on the same design. What kind of optimizations differ them. ?


Regards
Limitless_21
 

Both of them do the same thing i.e. they take an RTL and generate a netlist based on your constraints. The basic flow for both is also roughly the same. The difference will be in the quality of the final output(the timing & area performance) of the netlist. That may(or rather will) differ.
 

Hi,
As Sharath mentioned both tools do the same job but the quality of synthesis differs based on designs. One thing to point is that RC does not perform hold analysis whereas DC has certain options for hold analysis.

Also to get more insight you can view the following article.
https://www.deepchip.com/items/0492-01.html
 
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