SOC initialization sequence

Why it is important to verify SOC initialization sequence using SDF annotated post layout netlist ?

Well you want to garantee the power-up and the sequence till the processor(s) run(s), and with back-annotated timing, the result is more accurate, and with mix simulation (analog& digital) that's better also.

There has always been an argument on the necessity of gate-level simulation(GLS).

In theory, GLS is not needed AS LONG AS the logic "AND" of the following items is TRUE:
1) constraint files are extremely carefully designed and reviewed, and no constraint is either missing or loosened.
2) STA result is satisfactory, namely PT/PTSI(or the same kind of tool, like goldtime) is used to sign-off without timing violation.
3) Functional verification coverage is high enough(as to how high it should be, it depends on companies/teams).
As we can see, the above items are sometimes hard to achieve. For example, how do you guarantee item 1) for a complex chip design in scale of 50M-100M gates, with many clock domains? Therefore, if time permitted, GLS is usually preferred just to "gain some confidence" for the design to be taped out.
Another uncertainty is that power-gating related flow does not support functional-level simulation, cause some isolation cells don't even exist before post-layout. Hence GLS is employed sometime for power-gating flow check, although current power-gating supports from EDA vendors are not mature enough for some type of GLS.