kwagjj
Member level 1
after layout and DRC, LVS check and creating calibre file for post layout simulation, I realize that it doesn't seem to include the inductance caused by the metal lines.
I've read the documents that has the sheet resistance of metal lines but it doesn't have any info about inductance.
I wonder if the self/mutual inductance between metal lines are negligible. Is this why inductance is not considered?
I am currently designing an IC chip with 2.4GHz. The chip size is about 1.5mm x 0.9mm... Would even the longest metal line have considerable inductance?
I've read the documents that has the sheet resistance of metal lines but it doesn't have any info about inductance.
I wonder if the self/mutual inductance between metal lines are negligible. Is this why inductance is not considered?
I am currently designing an IC chip with 2.4GHz. The chip size is about 1.5mm x 0.9mm... Would even the longest metal line have considerable inductance?