vhdl inout alternative

can i use signal and do operation and assign signal to port declared as out.rather than using it as inout and use directly whats the difference? Suppose the program is for negative ramp if i use output 12 bit as inout i can do d<=d-1 but if i use d as out and use another signal to do ds<=ds-1 and then say d<=ds why is it not working

What is "negative RAM"?

inout has to be used for bidirectional ports that are also driven from the upper instance (the port must be tristated internally to allow this). Notice that internal bidirectional busses aren't possible in most hardware platforms, they must be emulated by the synthesis tool.

To allow read-back of an out port, you can declare it as buffer, or use an auxilary internal signal (like ds). It's not clear from your post what's "not working" with your code.

FvM said:

What is "negative RAM"?

inout has to be used for bidirectional ports that are also driven from the upper instance (the port must be tristated internally to allow this). Notice that internal bidirectional busses aren't possible in most hardware platforms, they must be emulated by the synthesis tool.

To allow read-back of an out port, you can declare it as buffer, or use an auxilary internal signal (like ds). It's not clear from your post what's "not working" with your code.

Click to expand...

i am doing my 2nd year graduation of electronics and communcation..
i have only basic knowledge...it is NEGATIVE RAMP WAVE GENERATOR sorry i wasnt specific i will post the code below

.

RAMP

my code in exam (i didnt get any output in exam in CRO )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rampwg is
Port ( clk,rst : in std_logic;
d : out std_logic_vector(11 downto 0));
end rampwg;

architecture Behavioral of rampwg is
signal clk_div:std_logic_vector(25 downto 0);
signal clkdiv:std_logic;
signal ds :std_logic_vector(11 downto 0);

begin
process(clk)
begin
if rising_edge(clk) then
clk_div<= clk_div+'1';
end if;
end process;
clkdiv<=clk_div(1);
process (clkdiv)
begin
if rst='1' then ds<=(others=>'0');
elsif rising_edge(clkdiv) then
ds<= ds-1;
end if;
end process;
d<=ds;

end Behavioral;




code in lab manual (i didnt remember that inout has to be used so i used above code)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rampwg is
Port ( clk,rst : in std_logic;
d : inout std_logic_vector(11 downto 0));
end rampwg;

architecture Behavioral of rampwg is
signal clk_div:std_logic_vector(25 downto 0);
signal clkdiv:std_logic;


begin
process(clk)
begin
if rising_edge(clk) then
clk_div<= clk_div+'1';
end if;
end process;
clkdiv<=clk_div(1);
process (clkdiv)
begin
if rst='1' then d<=(others=>'0');
elsif rising_edge(clkdiv) then
d<= d-1;
end if;
end process;


end Behavioral;

There's no reason to use inout for an output port. The first code will work, too.

I won't expect a divided clock construct (clkdiv) in a lab manual, because it's considered bad practice.

I don't understand how you test the design with a CRO, do you connect a DAC to the FPGA? Or is it a simulation?

you declared ds as a 12 bit vector but assigning only 8 bits in this statement
if rst='1' then ds<="00000000";and also initialize clk_div to default value.
signal clk_div:std_logic_vector(25 downto 0):=(others=>'0');and also include rst in sensitivity list for second process.

Not sure the code posted for the "lab manual" was correctly copied into the post as the ds <= "00000000"; isn't used nor is ds defined.

sorry bad typo....i corrected the code i did copy paste sorry...the program is dumped to fpga kit an with dac and CRO gives output ....the second code i declared inout but first i didnt....is both program correct

thanks for reply

Both the codes are correct functionally, but there are few things you must know..
reset is not in the sensitivity list of the second process.

its a bad practice to use a signal as a clock , as you are using clk_div as clk in the second process.
better way is -
add one more process
process (clk)
begin
if rising_edge(clk) then
clk_div_d <= clk_div ;
end if;
end process;

and instead of using rising_edge (clk_div)

write
process(clk, reset)
begin
if reset = '1' then
ds <= (others => '0')
elsif rising_edge(clk) then
if (clk_div and (not(clk_div_d) ) = '1' then
ds <= ds - 1;
end if;
end if;