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ASIC synthesis and routing

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rajavel.rv

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Hi, I am need a help for how Design flow of ASIC synthesis and routing will happen, and which tool is very useful for me to synthesis my HDL coding, and share the steps.

please share your knowledge for ASIC flow of design. If i can possible to see the RTL view and debugging the bug, its same like as a fpga tool or different.

Thanks & Regards
Rajavel Ashokraj
 

Synthesis is done using RTL compiler from cadence, Design Compiler (DC) from synopsys. Routing is done by PNR tools Cadence Encounter uses Nanorouter for routing. ICC also have it own routing engine. There are very good documents related to ASIC design are available at below link.

https://www.evlsi.com/viewtopic.php?f=19&t=81
 
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