VHDL code problem, need help ASAP !

library ieee;
use ieee.std_logic_1164.all;
entity data is
port ( LI,RI: in bit_vector ( 6 downto 0); sub1, sub2, sub3, sub4,delta: in bit_vector (6 downto 0);C1: in bit; x,yut bit);
end entity data ;

architecture logicvariable of data
is


signal s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s50,s51,s52,s53,s54,s55,s56,s57,s58,s59,s60,s61,s62,s63,s64,s65 :bit;

begin

s50 <= RI( 1 downto 0) & "00000";
s51 <= "00000000";
s0 <= s50 xor s51; -- first group
s1 <= s0 xor RI xor C1;
s2 <= sub1 xor delta xor C1;
s3 <= s2 xor s1;
s4 <= LI xor s3 xor C1;

s52 <= s4 ( 1 downto 0) & "00000";
s53 <= "00000000";
s5 <= s52 xor s53 ; -- second group
s6 <= s5 xor s4 xor C1;
s7 <= sub2 xor delta xor C1;
s8 <= s7 xor s6;
s9 <= RI xor s8 xor C1;

s54 <= s9( 1 downto 0) & "00000";
s55 <= "00000000";
s10 <= s54 xor s55; -- third group
s11 <= s10 xor s9 xor C1;
s12 <= sub3 xor delta xor C1;
s13 <= s12 xor s11;
s14 <= s4 xor s13 xor C1;

s56 <= s14( 1 downto 0) & "00000";
s57 <= "00000000";
s15 <= s56 xor s57; -- forth group
s16 <= s15 xor s14 xor C1;
s17 <= sub4 xor delta xor C1;
s18 <= s17 xor s16;
s19<= s9 xor s18 xor C1;

s58 <= s19( 1 downto 0) & "00000";
s59 <= "00000000";
s20 <= s58 xor s59; -- fifth group
s21 <= s20 xor s19 xor C1;
s22 <= sub1 xor delta xor C1;
s23 <= s22 xor s21;
s24 <= s23 xor s14 xor C1;

s60 <= s24( 1 downto 0) & "00000";
s61 <= "00000000";
s25 <= s60 xor s61; -- sixth group
s26 <= s25 xor s24 xor C1;
s27 <= sub2 xor delta xor C1;
s28 <= s27 xor s26;
s29 <= s19 xor s28 xor C1;

s62 <= s29( 1 downto 0) & "00000";
s63 <= "00000000";
s30 <= s62 xor s63; -- seventh group
s31 <= s30 xor s29 xor C1;
s32 <= sub3 xor delta xor C1;
s33 <= s32 xor s31;
s34 <= s33 xor s24 xor C1;

s64 <= s34 (1 downto 0) & "00000"; -- eight group
s65 <= "00000000";
s35 <= s64 xor s65;
s36 <= s35 xor s34 xor C1;
s37 <= sub4 xor delta xor C1;
s38 <= s37 xor s36;
s39 <= s38 xor s34 xor C1;


x <= s34;
y <= s39;

end architecture logicvariable;

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imbichie said:

Hi,
Can you try it after by adding these VHDL libraries :

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

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imbichie said:

Hi,
Can you try it after by adding these VHDL libraries :

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

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TrickyDicky said:

Apart from the fact that std_logic_arith and std_logic_unsigned are not standard VHDL libraries, and hence should not be used in any new code, they will not help you here as the OPs code is all bit_vectors.

OP, you need to post the whole code - the code snippet is not enough. The picture hides the definition of s50 and s51.

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TrickyDicky said:

You need to show the full code, so we can see how s50 and s51 are declared.
Post the full code in the forum, inside code or syntax tags.

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TrickyDicky said:

Editing existing posts is frowned upon btw.

- - - Updated - - -

the problem is that s50 and s51 are bits, not bit_vectors.

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alpha91 said:

so what should i do? i cannot make the output as signal ? i need to shift the input.

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kommu4946 said:

s1 <= s0 xor RI xor C1; change it to as like
s1 <= s0 xor RI xor ("000000" & C1);every where C1 is present.

Click to expand...

@TrickyDicky I forgot to mention That is after changing every signal to bit_vector except C1.

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kommu4946 said:

@TrickyDicky I forgot to mention That is after changing every signal to bit_vector except C1.

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FvM said:

So we are back to start: Show your code!

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TrickyDicky said:

Im getting deja vu: You cannot do a shit register with single bits, as s50 and s51 are declared. You need to use a bit-vector, ie. an array of bits.

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