some more analog layout questions

Hello,

Please help me with the following questions :

If EM fails at the metal to diffusion contact, let's say source/drain contact and we cannot play with the w/l or no of contacts , is there a way to fix EM there ?
In ESD protection scheme , we put diodes at inputs to clamp the voltage. Considering that, why can't antenna diode save from ESD ( it's also a similar scheme where we put diode on gate )?
How do we check if half-DRC rule at the IP boundary is met ?
What decides if shielding is to be done with VSS or VDD ?
What decides the flip chip AP-RDL routing width ?

Thanks in advance.

1) multiple contacts per diffusion

2) size matters and so do latchup rules

3) Never done a half verification

4) consequences of noise riding on that rail - try injecting
some and decide whether it's a "shield" or an "aggressor"

5) Your foundry sets min rules, your current / desired Q /
etc. drive it up from there.

sudeeps said:

How do we check if half-DRC rule at the IP boundary is met ?

Click to expand...

Full chip DRC will check for it and show. But if you want to be careful, extend the IP boundary ½ of all min. DRC rules' layer spacings.

dick_freebird said:

1) multiple contacts per diffusion

2) size matters and so do latchup rules

3) Never done a half verification

4) consequences of noise riding on that rail - try injecting
some and decide whether it's a "shield" or an "aggressor"

5) Your foundry sets min rules, your current / desired Q /
etc. drive it up from there.

Click to expand...

Thanks for the replies . Actually I have these concerns with your replies, if you can help :

1) As I said in the question I cannot alter the W/L or no of contacts per souce/drain then how can I achieve multiple contacts per diffusion ?

2) I didn't get it. If I use same size diodes in both the case, why do I need antenna then ?

Thanks

You ask whether an antenna diode can protect from ESD.
The answer is "no", because your premise of using equal
sized diodes is inappropriate. Antenna diodes are bare
minimum size to present minimum loading to internal nets.
ESD diodes are sized large for >1A pulsed current handling
without damage or drift. They also, in most technologies,
incorporate additional features for pin induced latchup
prevention that a "core" diode never subjected to isolation
forward-bias would not.

Please find the answers in below
1.---> Change the metal tapping point to avoid EM in your case. Since tool is assuming that, the first contact will taking all current but that is not the case.

2. --> Antenna diode are required to discharge the charges accumulated on metals during the fabrication process to avoid gate breakdown. This diodes will not functioning during operation just it will add reverse bias junction cap to gate.

ESD current will be 1A, so cannot handle the small diode. This event occurs when chip is not functioning.

Thanks,
basu

sudeeps said:

Thanks for the replies . Actually I have these concerns with your replies, if you can help :

1) As I said in the question I cannot alter the W/L or no of contacts per souce/drain then how can I achieve multiple contacts per diffusion ?

Thanks

Click to expand...

Hi,

try to use metal stack if you are allowed to do that..this will help you to reduce the EM effect..